Xilinx 7.1 and testbench error

Discussion in 'Software' started by boitsas, Jan 15, 2008.

  1. boitsas


    Jan 12, 2008
    Likes Received:
    Hello there,
    A have a problem in my design with Xilinx 7.1.All the modules are passing the check syntax and the synthesis compile but when i try to create a testbench it comes with an error

    Compiling vhdl file "C:/Xilinx/mikevavouras/fitness.vhd" in Library work.
    ERROR:HDLParsers:3014 - "C:/Xilinx/mikevavouras/fitness.vhd" Line 21. Library
    unit sizing is not available in library work.
    WARNING:HDLParsers:3481 - Library work has no units. Did not save reference file
    "C:/DOCUME~1/Boitsas/LOCALS~1/Temp/xil_3480_5/hdllib.ref" for it.
    vhdtdtfi:Declaration (Module top) not found.
    tdtfi(vhdl) completed with errors.
    Error creating test.vhd. Defaulting to boilerplate test bench.

    p.s: I use a package called sizing.vhd which is included in the project and in the library work and i use in all the modules

    Library work
    use work.sizing.ALL

    If anybody has a solution!!!!!

    thanks in advance.
    boitsas, Jan 15, 2008
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