Hello there,\r\nA have a problem in my design with Xilinx 7.1.All the modules are passing the check syntax and the synthesis compile but when i try to create a testbench it comes with an error\r\n\r\n\r\nCompiling vhdl file "C:/Xilinx/mikevavouras/fitness.vhd" in Library work.\r\nERROR:HDLParsers:3014 - "C:/Xilinx/mikevavouras/fitness.vhd" Line 21. Library\r\n unit sizing is not available in library work.\r\nWARNING:HDLParsers:3481 - Library work has no units. Did not save reference file\r\n "C:/DOCUME~1/Boitsas/LOCALS~1/Temp/xil_3480_5/hdllib.ref" for it.\r\nvhdtdtfi:Declaration (Module top) not found.\r\ntdtfi(vhdl) completed with errors.\r\nError creating test.vhd. Defaulting to boilerplate test bench.\r\n\r\n\r\n\r\n\r\np.s: I use a package called sizing.vhd which is included in the project and in the library work and i use in all the modules\r\n\r\nLibrary work\r\nuse work.sizing.ALL\r\n\r\n\r\n\r\nIf anybody has a solution!!!!!\r\n\r\nthanks in advance.