VHDL Register file-help needed for a student

Discussion in 'Hardware' started by draaknar, Sep 27, 2013.

  1. draaknar

    draaknar

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    library IEEE;
    use ieee.std_logic_1164.all;
    USE ieee.std_logic_signed.all;
    use work.all;
    use assembler_code.all;
    use cpu_package.all;

    ENTITY registerfil IS
    PORT(

    clk : IN std_logic;
    data_in : IN data_word;
    data_out_1 : OUT data_word;
    data_out_0 : OUT data_word;
    sel_in : IN std_logic_vector (1 downto 0);
    sel_out_1 : IN std_logic_vector (1 downto 0);
    sel_out_0 : IN std_logic_vector (1 downto 0);
    rw_reg : in std_logic);

    END ENTITY registerfil;

    ARCHITECTURE RTL of registerfil is
    type test_register is array(3 downto 0) of std_logic_vector(3 downto 0);
    signal regs:test_register;
    signal data_in_temp : std_logic_vector(data_size-1 downto 0);

    begin

    logic:process(rw_reg)

    begin

    if rw_reg= '0' then
    regs(conv_integer(sel_in))<= data_in_temp;
    end if ;
    data_out_1<= regs(conv_integer(sel_out_0));
    data_out_0<= regs(conv_integer(sel_out_1));

    end process;

    las_in: process (clk)

    begin

    if rising_edge(clk) then
    data_in_temp <= data_in; -- bättre om du skriver in i regs hä

    end if;

    end process;

    end RTL;




    Hello im new to vhdl, and my code works i can simulate it to but i get errors, and cant save my values in my register array. My main point is to save values in the register "regs that i have created but if feels buggy.. Could you give me some help or tips to make the code better ? My main point is to save values in the register "regs that i have created but if feels buggy.

    regards, John schaizar
     
    draaknar, Sep 27, 2013
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  2. draaknar

    draaknar

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    Ok, i got the answer .


    my sel_in(11) went to --> -2 and not 3 so it was two complement form, i just wrote unsigned before it and wuualaa..
     
    draaknar, Sep 27, 2013
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