VHDL " range=>'0' "

Discussion in 'Hardware' started by mali7, May 12, 2012.

  1. mali7

    mali7

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    Hello all! I'm new to VHDL and i need some help to understand a statement
    whitch uses range => '0' ; that's a part of the code

    architecture Behavioral of hb_fir is

    ..............
    ..............

    type tab_reg is array (K downto 0) of signed(15 downto 0)
    signal reg2 :tab_reg;

    .............
    .............
    reg2(1) <= (reg2(1)'range => '0'); whats this do?

    ............
    ............
    ............

    end Behavioral;
     
    mali7, May 12, 2012
    #1

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