VHDL - connection std_logic_vector with array of std_logic_vector

Discussion in 'Hardware' started by wsch, Oct 21, 2013.

  1. wsch

    wsch

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    Hi

    I have a type:

    noc_io_data is array (natural range <>, natural range <>) of std_logic_vector (SIZE dowto 0);

    that I need to connect with a:

    std_logic_vector

    How can I do this connection? Only with the assignment of the individual bits from the array to the vector?

    What syntax should I use?

    Thanks
     
    wsch, Oct 21, 2013
    #1

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