VHDL and EDK: Custom IP core containing an array as a port using EDK

Discussion in 'Hardware' started by allsey_1987, Oct 27, 2009.

  1. allsey_1987

    allsey_1987

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    I have my doubts that anyone will be able to help me on this one, but i give it a try anyway:

    I'm integrating a soft-core microblaze cpu into a design for a control system. I have created a custom IP core for the microblaze system which contains a number of registers with variable behaviour. the custom IP core makes use of the following array/data structure to group together 16 12bit unsigned numbers to make it easier to move this in and out of the entities.

    I have used the definitions as follows inside a package file to group these common signals into an array:
    Code:
    library ieee;
    use ieee.numeric_std.all;
    
    package custom_signals is
    	type cosine_wave is record
    		period, amplitude	: unsigned(11 downto 0);
    	end record;
    	
    	type cosine_waves is array (natural range 0 to 7) of cosine_wave;
    end package custom_signals;
    
    package body custom_signals is
    end package body custom_signals;
    
    Now the problem is when I integrate this hardware back into the microblaze design, and that into my top level design and view the Hardware Instiation Template for my microblaze, the object which should be of type cosine_waves shows up as a std_logic_vector(0 to 7)... array dimensions are correct but the rest i wacked... what to do...???

    Any knowledge regarding working with records and arrays as ports will also be greatly appreciated.
     
    allsey_1987, Oct 27, 2009
    #1
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