systemverilog/verilog variable length packed vector

Discussion in 'Hardware' started by veevee, May 7, 2014.

  1. veevee


    May 7, 2014
    Likes Received:

    Is it possible to give unconstrained vector (variable length width) at verilog/systemverilog interface?

    task parse_packed_struct
    input [] struct_data;


    There are multiple different kind of vectors of data and constraining the interface to some parameter (i.e input [MAX:0] struct_data;) seems unoptimal and not too nice for reuse point of view (if MAX is needed to be increased)
    veevee, May 7, 2014
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