I need help with a vhdl description

Discussion in 'Hardware' started by aarelovich, Oct 11, 2006.

  1. aarelovich

    aarelovich

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    I need to specify a synchronous reset in a counter. for that I have the two following descriptions:

    ASYCHRONOUS RESET
    ARCHITECTURE a OF prescaler IS
    SIGNAL counter: UNSIGNED(22 downto 0);
    BEGIN
    Conteo:
    PROCESS (Clk, Reset)
    BEGIN
    IF Reset = '0' THEN
    counter <= "00000000000000000000000";
    ELSIF (Clk'Event and Clk='1') THEN
    counter <= counter + "00000000000000000000001";
    END IF;
    END PROCESS conteo;


    SYCHRONOUS RESET
    ARCHITECTURE a OF prescaler IS
    SIGNAL counter: UNSIGNED(22 downto 0);
    BEGIN
    Conteo:
    PROCESS (Clk, Reset)
    BEGIN
    IF (Clk'Event and Clk='1') THEN
    IF Reset = '0' THEN
    counter <= "00000000000000000000000";
    ElSE
    counter <= counter + "00000000000000000000001";
    END IF;
    END IF;
    END PROCESS conteo;

    However the sychrounous reset that I use occupies 10 Logic cells more than the other description according to rpt file.

    Is there any other way to specify the sychronous reset tha makes for a smaller machine.?

    Thanks
     
    aarelovich, Oct 11, 2006
    #1
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