Greetings,\nIm trying to implement simple freq. divider in verilog on SPARTAN 3E FPGA.\nThe goal is to feed the device 10MHz on one of the inputs and have 5 different products of division on outputs of it. As I am new to verilog, I think I misunderstand the language. Simulation with the included testbench file does not work either. Would you point me in the right direction, what is wrong here? For my board I change the ports and have appropriate UCF file.\n input i_clk;\ninput i_Reset;\noutput o_Out;\n\nparameter Divisor = 4;\nparameter Bits = 2;\n\nreg [Bits-1 : 0] r_Count;\nreg o_Out;\n\nalways @ (posedge i_clk or posedge i_Reset)\n if (i_Reset) begin\n r_Count <= 0;\n o_Out <= 0;\n end\n else\n if (r_Count != Divisor - 1) begin\n r_Count <= r_Count + 1;\n o_Out <= 0;\n end\n else begin\n r_Count <= 0;\n o_Out <= 1;\n end\n\nendmodule\n\nHow do I assign an input from the port to i_clk? How do I assign o_out to output and reset to btn?\n\nThanks a lot!