Freq. divider in verilog

Discussion in 'Hardware' started by UCF, Oct 20, 2011.

  1. UCF

    UCF

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    Greetings,
    Im trying to implement simple freq. divider in verilog on SPARTAN 3E FPGA.
    The goal is to feed the device 10MHz on one of the inputs and have 5 different products of division on outputs of it. As I am new to verilog, I think I misunderstand the language. Simulation with the included testbench file does not work either. Would you point me in the right direction, what is wrong here? For my board I change the ports and have appropriate UCF file.
    input i_clk;
    input i_Reset;
    output o_Out;

    parameter Divisor = 4;
    parameter Bits = 2;

    reg [Bits-1 : 0] r_Count;
    reg o_Out;

    always @ (posedge i_clk or posedge i_Reset)
    if (i_Reset) begin
    r_Count <= 0;
    o_Out <= 0;
    end
    else
    if (r_Count != Divisor - 1) begin
    r_Count <= r_Count + 1;
    o_Out <= 0;
    end
    else begin
    r_Count <= 0;
    o_Out <= 1;
    end

    endmodule

    How do I assign an input from the port to i_clk? How do I assign o_out to output and reset to btn?

    Thanks a lot!
     
    UCF, Oct 20, 2011
    #1
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