Data transferred over a bridge on the falling edge of clock

Discussion in 'Hardware' started by debayan_p, May 14, 2014.

  1. debayan_p

    debayan_p

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    Dear all,

    I am debugging a data-conversion bridge. Here one of the input signals is connected inside the bridge directly to an output signal on the other of the bridge. There are no registered or combinatorial paths for this connection.

    I have a VHDL stmnt something like: mwait_o <= stall_i;

    However when I am running the test-bench, I see that the value of stall_i is being transferred to mwait_o at the falling edge of the clock and not immediately on the rising-edge or as soon as the value of stall_i changes (which should be the expected behavior as per my VHDL stmnt).

    Can anyone comment what could be the probable reason for this?

    Thanks,
    dpaul
     
    debayan_p, May 14, 2014
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  2. debayan_p

    debayan_p

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    Thread closed!

    Was a stupid mistake --- the i/p signal was missing from the sensitivity list!
     
    debayan_p, May 14, 2014
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