CALL FOR PAPERS\n\nISQED 2006, 7th International Symposium on\n\nQUALITY ELECTRONIC DESIGN\n\nMarch 27-29, 2006. San Jose, CA, USA\n\n[URL]http://www.isqed.org[/URL]\n\nISQED is the pioneer and leading international conference dealing with the \ndesign for manufacturability and quality issues front-to-back. ISQED spans \nthree days, Monday through Wednesday, in three parallel tracks, hosting near \n100 technical presentations, six keynote speakers, two-three panel \ndiscussions, workshops /tutorials and other informal meetings. Conference \nproceedings are published by IEEE Computer Society and hosted in the digital \nlibrary. Proceedings CD ROMs are published by ACM. In addition, continuing \nthe tradition of reaching a wider readership in the IC design community, \nISQED will continue to publish special issues in leading journals. The \nauthors of high quality papers will be invited to submit an extended version \nof their papers for the special journal issues.\n\nPapers are requested in the following areas\n===========================================\nA pioneer and leading multidisciplinary conference, ISQED accepts and \npromotes papers related to the design and manufacturing of quality-based \nintegrated circuits and systems, from design concept to production and all \nkey steps between. Authors are invited to submit papers in the various \ndisciplines of high level design, circuit design, test & verification, \ndesign automation tools; processes; and flows, device modeling, \nsemiconductor technology, and advance packaging. Authors are further \nencouraged to highlight the link between their subject of interest to the \noverall design flow chain and address the design quality aspects of the \nsubject (e.g.,. performance, power, yield, reliability, manufacturability, \ntime to market , and environmental considerations, etc.).\n\nDesign for Manufacturability & Quality (DFMQ)\n=============================================\nAnalysis, modeling, and abstraction of manufacturing process parameters and \neffects for highly predictable silicon performance. Design and synthesis of \nhigh complexity ICs: signal integrity, transmission line effects, OPC, \nphase shifting, and sub-wavelength lithography, manufacturing yield and \ntechnology capability. Design for diagnosability, defect detection and \ntolerance; self-diagnosis, calibration and repair. Design and \nmanufacturabilty issues for Digital, analog, mixed signal, RF, MEMS, \nopto-electronic, biochemical-electronic, and nanotechnology based ICs. \nRedundency and other yield improving techniques. Design quality definitions \nand standards; design quality metrics to track and assess the quality of \nelectronic circuit design, as well as the quality of the design process \nitself; design quality assurance techniques. Global, social, and economic \nimplications of design quality. Design metrics, methodologies and flows for \ncustom, semi-custom, ASIC, FPGA, RF, memory, networking circuit, etc. with \nemphasis on quality. Design metrics and quality standards for SoC, and SiP.\n\nPackage - Design Interactions & Co-Design (PDI)\n================================================\nConcurrent circuit and package design and effect on quality. Packaging \nelectrical and thermal modeling and simulation for improved quality of \nproduct. SoC versus system in a package (SiP): design and technology \nsolutions and tradeoffs; MCM and other packaging techniques; heat sink \ntechnology.\n\nDesign Verification and Design for Testability (DVFT)\n=====================================================\nHardware and Software, formal and simulation based design verification \ntechniques to ensure the functional correctness of hardware early in the \ndesign cycle. DFT and BIST for digital and SoC. DFT for analog/mixed-signal \nICs and systems-on-chip, DFT/BIST for memories. Test synthesis and \nsynthesis for testability. DFT economics, DFT case studies. DFT and ATE. \nFault diagnosis, IDDQ test, novel test methods, effectiveness of test \nmethods, fault models and ATPG, and DPPM prediction. SoC/IP testing \nstrategies.\n\nRobust Device, Interconnect, and Circuits (RDIC)\n================================================\nDevice, substrate, interconnect, circuit , and IP block modeling and \nsimulation techniques; quality metrics, model order reduction; CMOS, \nBipolar, and SiGe HBTs device modeling in the context of advanced digital, \nRF and high-speed circuits. Modeling and simulation of novel device and \ninterconnect concepts. Signal integrity analysis: coupling, inductive and \ncharge sharing noise; noise avoidance techniques. Power grid design, \nanalysis and optimization; timing analysis and optimization; thermal \nanalysis and design techniques for thermal management. Modeling statistical \nprocess variations to improve design margin and robustness, use of \nstatistical circuit simulators. Power-conscious design methodologies and \ntools; low power devices, circuits and systems; power-aware computing and \ncommunication; system-level power optimization and management. Design \ntechniques for leakage current management.\n\nEDA Methodologies, Tools, & IP Cores; Interoperability and Reuse(EDA)\n======================================================================\nEDA tools addressing design quality. Management of design process, design \nflows and design databases. EDA tools interoperability issues and \nimplications. Effect of emerging technologies, processes & devices on design \nflows, tools, and tool interoperability. Emerging EDA standards. EDA design \nmethodologies and tools that address issues which impact the quality of the \nrealization of designs into physical integrated circuits. IP modeling and \nabstraction. Design and maintenance of technology independent hard and soft \nIP blocks. Methods and tools for analysis, comparison and qualification of \nlibraries and hard IP blocks. Challenges and solutions of the integration, \ntesting, and qualifying of IP blocks from multiple vendors. Third party \ntesting of IP blocks. Risk management of IP reuse. IP authoring tools and \nmethodologies.\n\nPhysical Design, Methodologies & Tools (PDM)\n============================================\nPhysical synthesis flows for correct-by-construction quality silicon, \nimplementation of large SoC designs. Tool frameworks and datamodels for \ntightly integrated incremental synthesis, placement, routing, timing \nanalysis and verification. Placement, optimization, and routing techniques \nfor noise sensitivity reduction and fixing. Algorithms and flows for \nharnessing crosstalk-delay during physical synthesis. Tool flows and \ntechniques for antenna rule and electromigration rule avoidance and fixing. \nSpare-cell strategies for ECO, decoupling capacitance and antenna rule \nfixing. Planning tools for predictable high-current, low-voltage power \ndistribution. Reliable clock tree generation and clock distribution \nmethodologies for Gigahertz designs. EDA tools, design techniques, and \nmethodologies, dealing with issues such as: timing closure, R, L, C \nextraction, ground/Vdd bounce, signal noise/cross-talk /substrate noise, \nvoltage drop, power rail integrity, electromigration, hot carriers, EOS/ESD, \nplasma induced damage and other yield limiting effects, high frequency \neffects, thermal effects, power estimation, EMI/EMC, proximity correction & \nphase shift methods, verification (layout, circuit, function, etc.).\n\nEffects of Technology on IC Design, Performance, Reliability, and Yield \n(TRD)\n==============================================================================\nEffect of emerging processes & devices on design's time to market, yield, \nreliability, and quality. Emerging issues in DSM CMOS: e.g. sub-threshold \nleakage, gate leakage, technology road mapping and technology extrapolation \ntechniques. New and novel technologies such as SOI, Double-Gate(DG)-MOSFET, \nGate-All-Around (GAA)-MOSFET, Vertical-MOSFET, strained CMOS, high-bandwidth \nmetallization, etc. Challenges of mixed-signal design in digital CMOS or \nBiCMOS technology, including issues of substrate coupling, cross-talk and \npower supply noise. Significance of reliability effects such as gate oxide \nintegrity, electromigration, ESD, etc., in relation to electronic design. \nImpacts of process technologies on circuit design and capabilities (e.g. \nlow-Vt transistors versus increased off-state leakages) and the accuracy, \nuse and implementation of SPICE models that faithfully reflect process \ntechnologies. Successful applications of TCAD to circuit design.\n\nSystem-level Design, Methodologies & Tools (SDM)\n================================================\nGlobal, Social, and Economical Implications of Electronic System and Design \nQuality. Emerging standards and regulations influencing system quality. \nEmerging system-level design paradigms, methods and tools aiming at quality. \nSystem-level design process and flow management. System-level design \nmodeling, analysis and synthesis, estimation and verification for correct \nhigh-quality hardware/software systems. Responsive, secure, and defect \ntolerant systems. New concepts, methods and tools addressing system-level \ndesign complexity and multitude of aspects. Methods and tools addressing the \nusage of technology information and manufacturing feedback in the system-, \nRTL- and logic level design. The influence of the nanometer technologies' \n(application-dependent) yield and other issues on the system-, RTL- and \nlogic-level design. System-level trade-off analysis and multi-objective \n(yield, power, delay, area .) optimization. Effective and efficient design, \nimplementation, analysis and validation of large SoCs integrating IP blocks \nfrom multiple vendors.\n\n\nSubmission of Papers\n====================\nPaper submission must be done on-line via the conference web site at \n[URL="http://www.isqed.org"]www.isqed.org[/URL]. Authors should submit FULL-LENGTH, original, unpublished \npapers (Minimum 4, maximum 6 pages) along with an abstract of about 200 \nwords. Please check the as-printed appearance of your paper before \nuploading. To permit a blind review, do not include name(s) or \naffiliation(s) of the author(s) on the manuscript and abstract. The \ncomplete contact author information needs to be entered separately. When \nready to submit your paper have the following information ready:\n\nI Title of the paper\nII Name, affiliation, complete mailing address and phone, fax, and email of \nthe first author\nIII Name, affiliations, city, state, country of additional authors\nIV Person to whom correspondence should be sent, if other than the 1st \nauthor\nV Suggested area (as listed above)\n\nThe guidelines for the final paper format are provided on the conference web \nsite at [URL="http://www.isqed.org"]www.isqed.org[/URL]. Authors of the submitted papers must register and \nattend the conference for their paper to be published. Please note the \nfollowing important dates:\n\nPaper Submission Deadline\n\nOctober 26, 2005\n\nAcceptance Notifications\n\nNovember 1, 2005\n\nFinal Camera-Ready paper\nJanurary 3, 2006\n\n\nAbout ISQED\n===========\nThe International Symposium on Quality Electronic Design (ISQED), is a \npremier Design & Design Automation conference, aimed at bridging the gap \nbetween and integration of, electronic design tools and processes, \nintegrated circuit technologies, processes & manufacturing, to achieve \ndesign quality. ISQED is the pioneer and leading conference dealing with \ndesign for manufacturability and quality issues front-to-back. The \nconference provides a forum to present and exchange ideas and to promote the \nresearch, development, and application of design techniques & methods, \ndesign processes, and EDA design methodologies and tools that address issues \nwhich impact the quality of the realization of designs into physical \nintegrated circuits. The conference attendees are primarily designers of the \nVLSI circuits & systems (IP & SoC), those involved in the research, \ndevelopment, and application of EDA/CAD Tools & design flows, process/device \ntechnologists, and semiconductor manufacturing specialists including \nequipment vendors. ISQED emphasizes a holistic approach toward design \nquality and intends to highlight and accelerate cooperation among the IC \nDesign, EDA, Semiconductor Process Technology and Manufacturing communities.