Assign default values to generated VHDL signals

I use generate statements to make signals and instances of registers and other components. Individual load signals to the registers are only driven at certain points during the algorithm and outside the generate leaving the remaining signals not driven and simulating to a U value. Even when a register is loaded the load returns to U so the data does not remain.

Is there a way to initialize the generated load (ld) so that it does not assume a value of U.

Thanks

subtype Depth128 is integer range 0 to 127;
type array_2 is array(Depth128) of std_logic_vector (1 downto 0);
type load is array (Depth128) of std_logic;
type age is array (Depth128) of std_logic;
type array_48 is array(Depth128) of std_logic_vector (47 downto 0);
type array_7 is array(Depth128) of std_logic_vector (6 downto 0);

signal ld, loaded, sel : load;
signal A, A0_R, A1_R, match, not_a1, A0, A1, A0EXORA1 : age;
signal D : array_48;
signal add_number : array_7;

BEGIN
New_SA <= New_SA_r;
overflow_error <= overflow_error_i;

GEN_Tables : for M in 0 to 127 generate

Address_Storage : REG48
PORT MAP(
CLK => CLK,
RST => RST,
ld => ld(M), --Signal driven outside generate
di => data_in,
do => D(M)
);

New_SA_i <= '1' when Match(M) = '0' AND SA_Rdy = '1' else '0'; -- it's not in any of them

.
.
.

end generate;

ld(count) <= '1' when SEQ_Rdy = '1' AND New_SA_r = '1' AND full = '0' else 'U'; --load next register

ld(highest) <= '1' when SEQ_Rdy = '1' AND New_SA_r = '1' AND full = '1' AND overflow_error_i = '0' else 'U'; --Replaces aged SA