AMBA AHB Master - Write Latency Problems

Discussion in 'Hardware' started by DMC_606, Oct 21, 2014.

  1. DMC_606

    DMC_606

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    I'm using a SmartFusion2 Actel FPGA's FDDR memory controller and its an AMBA AHB (or AXI) slave. Since the FDDR3 bus is 32bits wide, I've opted for the simpler, 32bit site AHB bus. I must therefore write an AHB master in the FPGA logic.

    I am writing data from an embedded FIFO/DPRAMs into the FDDR as a temporary data buffer/circular buffer. This makes addresses always sequential. I am planning on writing a single long sequential access of ~2KB each time to empty the FIFO/DPRAM into the FDDR.

    I'm finding the AHB write bus access a BIG problem because of the low latency if PREADY is asserted by the slave. I could use Actel's CoreGEN FIFO but I'd have to use FWFT to overcome the latency. This works in simulation except for the fact that when the FIFO_RD signal is de-asserted, the FIFO output is not paused, but goes XX and this breaks the bus protocol for the next cycle (hard to explain in words). (I would not have this problem if it were a Xilinx FIFO and I'm finding bugs in Actels FIFO implementation - web case raised)


    Another way of doing it and I really don't want to (because it takes more FPGA FFs and is not bandwidth efficient) is to prefetch 4x32bit words then kick off a 4 word AHB write. I'd have all 4 words on a mux so latency will not be a problem. Whilst this is being written, I fetch the next 4 words. This will take 256 FFs to shift and load like a shift register and I have to break the AHB accesses to bursts of 4 and this will have some overhead between the cycles.

    Latency with a BRAM and address counter is too long (2 clock cycles). I can delay the AHB writes to allow for this delay at the start of the burst write, but that darn HREADY scuppers the plan as it "stalls" the pipeline.

    There must be a way of doing this..... its driving me crazy!

    Thanks
    Dave
     
    DMC_606, Oct 21, 2014
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