Altera Soft Core parallel tasking? Possible

Discussion in 'Hardware' started by bbiandov, Dec 2, 2006.

  1. bbiandov


    Sep 24, 2006
    Likes Received:

    I'm curious if this can be achieved on the C2 series - the idea is as simple as it might be utopian: can the fpga execute parallel events. And I mean truly parallel where one doesn’t see the top-to-bottom wave of delay. Sure I have never "seen it" as I don’t have million dollar turf analyzer but my curiosity is driven by the idea of protyping a very simple soft core in verilog, well for the lack of more fancy sounding name I mean a real basic instruction set and registers but in a truly parallel environment - such as parallel load from memory and parallel output to memory, but since all cores are on the same clock one could bead oneself in the chest for achieving >*1 environment, No?

    bbiandov, Dec 2, 2006
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