xilinx Bram

Discussion in 'Hardware' started by lastval, Oct 8, 2007.

  1. lastval

    lastval

    Joined:
    Oct 8, 2007
    Messages:
    2
    Hello all,

    I am using a Bram in an FPGA Design. The port A of the Bram is connected to an DSOCM controller, the other port B it says is not connected. I am making the ports in PORTB of Bram external and through a VHDL testbench i am loading he Ram with data to a specific address. The think is that this is not loading the data because port B seems inactive.

    do you know what i have to do in order to use (activate) the PortB of the Bram attached to an OCM bus?

    regards
    lastval, Oct 8, 2007
    #1
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Silverstrand

    Bram Cohen woos Hollywood with Bit Torrent

    Silverstrand, Aug 2, 2005, in forum: Front Page News
    Replies:
    0
    Views:
    682
    Silverstrand
    Aug 2, 2005
  2. amanpervaiz

    VHDL (Assigning pins in xilinx)

    amanpervaiz, Nov 7, 2006, in forum: Hardware
    Replies:
    3
    Views:
    1,780
    bbiandov
    Dec 2, 2006
  3. JayTee

    xilinx ISE8.2 error: XST779

    JayTee, Jul 11, 2007, in forum: Hardware
    Replies:
    1
    Views:
    676
    sridar
    Jul 11, 2007
  4. zoki111

    Using BRAM in state machines

    zoki111, Sep 18, 2007, in forum: Hardware
    Replies:
    0
    Views:
    958
    zoki111
    Sep 18, 2007
  5. boitsas

    Xilinx 7.1 and testbench error

    boitsas, Jan 15, 2008, in forum: Software
    Replies:
    0
    Views:
    1,259
    boitsas
    Jan 15, 2008
Loading...

Share This Page