Why should we use pipelining in FPGA?

Discussion in 'Hardware' started by shaiko, Sep 26, 2011.

  1. shaiko

    shaiko

    Joined:
    Sep 9, 2011
    Messages:
    3
    Hello people,
    I've read an interesting post a few days ago...

    Basically, it suggests that when doing logic operation that are time consuming - we should use pipelining.
    For example, if we want to multyply four 32 bit wide vectors (A,B,C,D) and move the result to vector Z.

    We shouldn't do Z <= A*B*C*D;

    but rather:

    PROCESS(Clk)
    BEGIN
    if(rising_edge(Clk)) then
    --Implement the pipeline stages using a for loop and case statement.
    --'i' is the stage number here.
    --The multiplication is done in 3 stages here.
    for i in 0 to 2 loop
    case i is
    when 0 => temp1 <= A*B;
    when 1 => temp2 <= B*C;
    when 2 => Z <= C*D;
    when others => null;
    end case;
    end loop;
    end if;
    END PROCESS;



    What I don't understand:
    If we consider the first example (Z<=A*B*C*D) after some delay and "settling time" - the correct result of Z will arrive at the end. It will be "glitchy" - but only for a very short time!
    After the "settling time" the product Z will be stable!

    So, why should we pipeline?
     
    shaiko, Sep 26, 2011
    #1
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