what does this error means in vhdl(xilinx)

Discussion in 'Software' started by vhdl-fpga, Nov 19, 2009.

  1. vhdl-fpga

    vhdl-fpga

    Joined:
    Nov 19, 2009
    Messages:
    1
    Running ISim simulation engine ...
    ERROR:Simulator:29 - at 0 ns : in arctest(testbench_arch), file
    C:/Xilinx92i/arch/arctest.vhw: Default port map for entity arc to component
    arc connects std_ulogic type local port C2 of the component to BIT type port
    of the entity.
    ERROR:Simulator:29 - at 0 ns :
    This is a Lite version of ISE Simulator.

    plz do reply asap
    :hmm2:
    :dontknow: :dontknow:
    vhdl-fpga, Nov 19, 2009
    #1
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