vhdl

Discussion in 'The Lounge' started by ravi B, Jul 30, 2012.

  1. ravi B

    ravi B

    Joined:
    Jul 30, 2012
    Messages:
    1
    hi,
    help me
    how can i have std_logic_vector of type real.means each bit in the vector should able to store real value.
    ravi B, Jul 30, 2012
    #1
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