VHDL

Discussion in 'Software' started by s.arthi, Nov 18, 2011.

  1. s.arthi

    s.arthi

    Joined:
    Nov 18, 2011
    Messages:
    1
    Hi..

    I have doubt in my project...
    how to write in VHDL... the runs of zeroes stop with one comes...
    like...eg: 00001 001
    and finally i count the zeroes...

    for the above eg: 4 2

    i tried this .....can u tell this would be right?

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    use ieee.std_logic_arith.all;

    entity sample is
    port( b0: inout std_logic_vector(13 downto 0):="10110000000010";
    count0:eek:ut std_logic_vector(13 downto 0);
    count1: out bit;
    reset,clk: in std_logic);
    end sample;

    architecture beh of sample is
    signal a0: std_logic_vector(13 downto 0);
    --constant c: integer := 1;

    begin
    process(clk,reset)
    variable cnt0 : std_logic_vector(13 downto 0);--:=(others=>'0');
    variable cnt1 : std_logic;

    begin
    if reset='0' then
    a0<=(others=>'0');
    elsif clk='1' and clk'event then
    a0<=b0;

    end if;
    cnt0:=(others=>'0');
    for i in 0 to 13 loop
    if a0(i) = '0' then
    cnt0:= cnt0 + 1;
    end if;
    if a0(i) ='1' then
    cnt1 := '1';
    end if;
    end loop;
    count0 <= cnt0;
    count1 <= '1';
    end process;
    end;
    Last edited: Nov 20, 2011
    s.arthi, Nov 18, 2011
    #1
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