vhdl+signal inistilization problem

Discussion in 'Hardware' started by NIOS, Nov 26, 2008.

  1. NIOS

    NIOS

    Joined:
    Nov 24, 2008
    Messages:
    2
    hello,
    iam actually working on a vhdl code that contains an FSM and i have a problem of initilization of one of the signals that iam using

    iam using a process ,i initialized this signal

    if(rst='1') then

    signal name<=(others=>'0'));

    but in the simulation this signal is XXXXXXXX when rst='1' and even after
     
    NIOS, Nov 26, 2008
    #1
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  2. NIOS

    NIOS

    Joined:
    Nov 24, 2008
    Messages:
    2
    the signal that i am talking about is an output not an internal signal
     
    NIOS, Nov 26, 2008
    #2
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