VHDL " range=>'0' "

Discussion in 'Hardware' started by mali7, May 12, 2012.

  1. mali7

    mali7

    Joined:
    May 12, 2012
    Messages:
    1
    Hello all! I'm new to VHDL and i need some help to understand a statement
    whitch uses range => '0' ; that's a part of the code

    architecture Behavioral of hb_fir is

    ..............
    ..............

    type tab_reg is array (K downto 0) of signed(15 downto 0)
    signal reg2 :tab_reg;

    .............
    .............
    reg2(1) <= (reg2(1)'range => '0'); whats this do?

    ............
    ............
    ............

    end Behavioral;
    mali7, May 12, 2012
    #1
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. asapanya

    Vhdl Coding

    asapanya, Mar 8, 2006, in forum: Hardware
    Replies:
    12
    Views:
    3,071
    bigal
    May 7, 2007
  2. Elyada Jacobsen

    I want to build RAM in vhdl

    Elyada Jacobsen, Aug 9, 2006, in forum: Hardware
    Replies:
    0
    Views:
    750
    Elyada Jacobsen
    Aug 9, 2006
  3. aarelovich

    I need help with a vhdl description

    aarelovich, Oct 11, 2006, in forum: Hardware
    Replies:
    0
    Views:
    724
    aarelovich
    Oct 11, 2006
  4. ohaqqi

    VHDL sll shift question

    ohaqqi, Oct 16, 2006, in forum: Hardware
    Replies:
    5
    Views:
    22,954
    tranhuuthu991990
    May 13, 2012
  5. becool_nikks
    Replies:
    0
    Views:
    1,975
    becool_nikks
    Mar 6, 2009
Loading...

Share This Page