VHDL Help

Discussion in 'Software' started by mahdoum, Dec 16, 2007.

  1. mahdoum

    mahdoum

    Joined:
    Dec 16, 2007
    Messages:
    1
    Hello,

    I'm new to ModelSIM and writing VHDL. I've got the below code giving me the error

    "adder.vhd(54): Actual (function call "f") for formal "b" is not a globally static expression."

    Here's the code

    Code:
    library ieee;
    use ieee.std_logic_1164.all;
    
    entity adder is
        port (  A : in std_logic_vector (3 downto 0);
                B : in std_logic_vector (3 downto 0);
                S : out std_logic_vector (3 downto 0);
                C : out std_logic
              );
    end adder;
    
    architecture struct of adder is
       
       component a_7483A
           port (
               A   :   in std_logic_vector (3 downto 0);
               B   :   in std_logic_vector (3 downto 0);
               C0  :   in std_logic;
               S   :   out std_logic_vector (3 downto 0);
               C4  :   out std_logic
           );
       end component;
       
    function f(S : std_logic_vector; C : std_logic) return std_logic_vector is
       
       begin
       
          if ((S(3) = '1' AND S(2) = '1') 
            OR ((S(3) = '1' AND S(1) = '1') OR (S(3) ='1' AND S(1) = '1' AND S(0) = '1'))
            OR (C = '1'))
            then
          
              return "0110";
        
          else 
              return "0000";
              
          end if; 
       
       end;
       
      
       signal S2 : STD_LOGIC_VECTOR(3 downto 0);
       signal C2 : STD_LOGIC;
       
       begin
    
           U1 : a_7483A port map (A, B, '0', S2, C2);
           U2 : a_7483A port map (S2, f(S2, C2), C2, S, C);  
           
     end struct;
    
    Hope someone can help... Thanks
    mahdoum, Dec 16, 2007
    #1
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