vhdl code for serial RAM

Discussion in 'General Computer Support' started by preithikashap, Jun 15, 2010.

  1. preithikashap

    preithikashap

    Joined:
    Jun 15, 2010
    Messages:
    1
    hiii

    i need a vhdl code for a serial ram (ram stores a 16 bit data and it shold output the data serially )code for my work immediately. please please can some one help me write the code.

    its really urgent. thanks in advance.
     
    preithikashap, Jun 15, 2010
    #1
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  2. preithikashap

    faust861

    Joined:
    Jun 23, 2010
    Messages:
    1
    I would do that like this:

    library ieee;
    use ieee.std_logic_1164.all;

    entity serial_ram is
    generic (
    n : integer := 16
    );
    port (
    data : in std_logic;
    clk : in std_logic;
    en_write : in std_logic;
    en_read : in std_logic;
    q: out std_logic
    );
    end;

    architecture behavioral of serial_ram is

    signal memo : std_logic_vector(n-1 downto 0);

    begin

    write_data : process(clk,en_write)
    variable i : integer := 0;
    begin
    if (rising_edge(clk) and en_write = '1') then
    memo(i) <= data;
    i := i+1;
    end if;
    if (i=n) then
    i := 0;
    end if;
    end process;

    read_data : process(clk,en_read)
    variable k : integer := 0;
    begin
    if (rising_edge(clk) and en_read = '1') then
    q <= memo(k);
    k := k+1;
    end if;
    if (k=n) then
    k := 0;
    end if;
    end process;

    end behavioral;

    I did it in 5 minutes, I don't think it's the best implementation but with a few simulation you can discover how to implement the best functionalities for your use.
    For example, you have to read or write, never doing both...if both enables are '1' this Ram doesn't work as you wish.
    Another thing, maybe the variables in the processes can annoy you...maybe you will prefer signals.
    You must simulate and try.

    Bye
     
    faust861, Jun 23, 2010
    #2
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