VHDL - Arbitrary Data Type

Discussion in 'Hardware' started by vino_TUM, Mar 20, 2012.

  1. vino_TUM

    vino_TUM

    Joined:
    Nov 19, 2011
    Messages:
    1
    Location:
    Munich, Germany
    Hi,

    I am having a problem in VHDL related to Component declaration.

    Bit width (a generic) of a port signal of type std_logic_vector is not visible to the module where it is
    declared as component and so I am getting a compilation error.

    How can I make the bit_width/data_type of the port signal generic while declaration and
    refine it during instantiation ?

    Thanks in advance ....

    Regards
    Vino
     
    vino_TUM, Mar 20, 2012
    #1
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  2. vino_TUM

    Nader Ilahi

    Joined:
    Jul 5, 2012
    Messages:
    2
    Hello Vino ,

    I need more details to confirm that I have understood you , would you please provide the code
    that cause the issue .otherwise when you make an instantiation of a component you shoud instantiate the generic aswell in order to be recognized .

    Nader
     
    Nader Ilahi, Jul 5, 2012
    #2
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