Verilog warning - output pins are stuck at GND

Discussion in 'Software' started by KyoukaNg, Oct 13, 2013.

  1. KyoukaNg

    KyoukaNg

    Joined:
    Oct 13, 2013
    Messages:
    1
    Location:
    melaka
    Hi,

    I've a few of questions.
    After i compile my verilog code in quartus2, the are warnings written as "output pins are stuck at GND". How can i solve this? Is it necessary to solve all the warning?

    My code is like this
    #############################################################################
    always@*
    if (reset)
    output = 0;
    #############################################################################
     
    KyoukaNg, Oct 13, 2013
    #1
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