synthesizing asynchronous state machines with Synplify_pro

Discussion in 'Hardware' started by vishali, Mar 22, 2007.

  1. vishali

    vishali

    Joined:
    Mar 22, 2007
    Messages:
    1
    Hi,
    I am trying to synthesize an asynchronous state machine in VHDL with the Synplify_pro tool. The reference manual contains instructions for that but I don't understand what I have to do. For reference, the instructions from the manual:

    "Create a netlist of the technology primitives from the target library for

    your technology vendor. Any instantiated primitives that are left in the

    netlist are not removed during optimization."

    - Does anyone have an idea what exactly I have to do?

    Thanks in advance,
    Vishali
     
    vishali, Mar 22, 2007
    #1
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