Synthesizable VHDL

Discussion in 'Hardware' started by shaiko, Sep 14, 2011.

  1. shaiko

    shaiko

    Joined:
    Sep 9, 2011
    Messages:
    3
    Hello people,

    Can the following VHDL code be synthesized?

    "input <= (conv_integer(number) => '1', others => '0');"

    notes:
    1."input" is defined as an std_logic_vector(15 downto 0) signal.
    2."number" is defined an integer signal with a range of 0 to 15 ("number" isn't a constant).
     
    shaiko, Sep 14, 2011
    #1
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