synthesis error

Discussion in 'Hardware' started by sekhar_kollati, Nov 13, 2007.

  1. sekhar_kollati

    sekhar_kollati

    Joined:
    Nov 7, 2007
    Messages:
    1
    when iam synthesizing this code i am getting these errors
    d" line 58: Index value(s) does not match array range, simulation mismatch.
    WARNING:Xst:790 - "C:/Xilinx/proj1/alg.vhd" line 58: Index value(s) does not match array range, simulation mismatch.
    WARNING:Xst:790 - "C:/Xilinx/proj1/alg.vhd" line 60: Index value(s) does not match array range, simulation mismatch.
    WARNING:Xst:790 - "C:/Xilinx/proj1/alg.vhd" line 60: Index value(s) does not match array range, simulation mismatch.
    WARNING:Xst:790 - "C:/Xilinx/proj1/alg.vhd" line 57: Index value(s) does not match array range, simulation mismatch.
    WARNING:Xst:790 - "C:/Xilinx/proj1/alg.vhd" line 58: Index value(s) does not match array range, simulation mismatch.
    WARNING:Xst:790 - "C:/Xilinx/proj1/alg.vhd" line 58: Index value(s) does not match array range, simulation mismatch.
    WARNING:Xst:790 - "C:/Xilinx/proj1/alg.vhd" line 60: Index value(s) does not match array range, simulation mismatch.
    WARNING:Xst:790 - "C:/Xilinx/proj1/alg.vhd" line 60: Index value(s) does not match array range, simulation mismatch.


    code is
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use work.pack1.all;
    entity cn1 is
    port(y:in mat;s,t:in integer range 0 to 5;o: out mat1);
    end cn1;
    architecture cn1 of cn1 is
    begin
    process(y,s,t)
    variable a:a1;
    variable i,k,min:integer range -5 to 99;
    variable d:mat;
    variable path:mat1;
    variable p:a1;
    begin
    --- assigning i/p y--> d
    for i in 0 to n-1 loop
    for j in 0 to n-1 loop
    d(i,j):=y(i,j);
    end loop;
    end loop;

    --intialisation of all nodes
    for i in 0 to n-1 loop
    a(i).pre:=-1;
    a(i).len:=inf;
    a(i).lab:=ten;
    end loop;

    a(t).len:=0;
    a(t).lab:=per;
    k:=t;

    -- calculating shotest path
    l1:loop
    for i in 0 to n-1 loop
    if((d(k,i)/=0) and (a(i).lab=ten)) then
    if ((a(k).len+d(k,i))<(a(i).len)) then
    a(i).pre:=k;
    a(i).len:=(a(k).len + d(k,i));
    end if;
    end if;
    end loop;
    k:=0;
    min:=inf;
    for i in 0 to n-1 loop
    if((a(i).lab=ten) and (a(i).len<min))then
    min:=a(i).len;
    k:=i;
    -- a(i).pre:=k; --extra
    end if;
    end loop;
    a(k).lab:=per;
    exit when (k=s);
    end loop l1;
    --end loop;
    i:=0;
    k:=s;
    -- l2:loop
    -- path(i):=k;
    -- i:=i+1;
    -- k:=a(i).pre;
    -- exit when (k<=0);
    -- end loop l2;
    for i in 0 to n-1 loop
    if(k>=0) then
    path(i):=k;
    k:=a(k).pre;
    end if;
    end loop;


    for i in 0 to n-1 loop
    o(i)<=path(i);
    end loop;
    --o<=path;
    end process;
    end architecture ;


    package:
    package pack1 is
    constant n:integer:=3; --no of nodes
    constant inf:integer:=99; ---no connection
    type x is (per,ten); ---perm/fixed ,,enum type
    type sekhar is
    record
    pre:integer;
    len:integer;
    lab:x;
    end record;
    type a1 is array( 0 to n-1) of sekhar; --creating n records
    -- type a1ptr is access a1;
    type mat is array (0 to n-1, 0 to n-1) of integer range -2 to 99;
    type mat1 is array (0 to n-1) of integer range -2 to 99;
    end pack1;
    package body pack1 is
    end pack1;
    and when adding test bench waveform it will automatically shutdowns
    please give me suggestions
    sekhar_kollati, Nov 13, 2007
    #1
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