RWM MEMORY with latches-help vhdl???

Discussion in 'Hardware' started by draaknar, Sep 30, 2013.

  1. draaknar

    draaknar

    Joined:
    Sep 26, 2013
    Messages:
    3
    library ieee;
    use IEEE.std_logic_1164.all;
    use ieee.numeric_std.all;

    use work.assembler_code.all;
    use work.cpu_package.all;



    ENTITY RW_MEMORY IS
    PORT( adr : IN adress_bus;
    data : INOUT data_bus;
    clk : IN std_logic;
    ce : IN std_logic; -- active low
    rw : IN std_logic); -- read on high
    END ENTITY RW_MEMORY;
    ARCHITECTURE Behaviour OF RW_MEMORY IS

    type rwm_type is array(0 to 2**(adress_bus'length)-1) of std_logic_vector(3 downto 0);

    signal regs: rwm_type:=(others=>(others=> '0'));
    signal test: std_logic_vector(1 downto 0);
    signal data_temp: std_logic_vector(3 downto 0);
    begin

    test <= ce&rw; --This is my signal which i use for ce and rw together.

    process(test,data_temp)

    begin

    if test ="00" then
    data_temp <= data;
    elsif test= "01" then
    data <= regs(to_integer(unsigned(adr)));
    else
    data <= (others => 'Z');
    data_temp <= (others => '0');
    end if;

    end process;





    test1: process(clk)
    begin
    if rising_edge(clk) then
    if test = "00" then
    regs(to_integer(unsigned(adr))) <= data_temp;
    end if;
    end if;
    end process;


    end Behaviour;



    Hello, i got alot of latches wich i dont know how to remove, ive tried all kind of methods to remove the latches, but i cant get anywhere. The big problem here is that i get inferring latches for data and data temp.


    Note that when test is "00" (write-mode ) it will just write when we clock and the value it writes is the data_temp which is equal to data. I would be very grateful if u gave me some hints or feedback to solve this problem and make the code Synthesizable.

    regards

    John Schaizar
     
    draaknar, Sep 30, 2013
    #1
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