quartusII simulation ok but pins stuck at vcc of gnd

Discussion in 'Software' started by Davg, May 15, 2014.

  1. Davg

    Davg

    Joined:
    Sep 5, 2012
    Messages:
    3
    Hi. Thanks to all of you out there who are helping to solve problems. Now here's one that I need help with....

    I've created a component in VHDL which simulates and works properly when used in Altera-Modelsim with a testbench file.

    The component I have created also calls up a sub-component, a dual-port RAM created by Mega-wizard pulg-in.

    When I try to compile my top-level design (which calls up my user component, which in turn calls up the dual port RAM) I get the error message 'pins stuck at VCC or GND for all the outputs of the dual port RAM.

    In the toplevel design I call up my user component which, for test purposes has all its I/Os mapped straight to device pins (directly or via a STD_LOGIC_VECTOR to/from integer conversion), so that no inputs should be fixed at vcc or gnd.

    Therefore no outputs should be fixed at vcc or gnd.
    So why does my design simulate perfectly okay and yet give these warnings when compiled on quartusII?

    Some of the outputs from my component are actually changing and not stuck at vcc or gnd, but all of the q outputs from the dual port ram are stuck at vcc or gnd

    Any ideas??? thanks!!
    Davg, May 15, 2014
    #1
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  2. Davg

    Davg

    Joined:
    Sep 5, 2012
    Messages:
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    I have got around this problem now..
    It seems that there is a bug with the Dual port RAM (1 write/ 1 read)

    So instead use the true dual port RAM (2 read/write ports) -this works, and ignore the ports you don't need.
    Davg, May 16, 2014
    #2
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  3. Davg

    Davg

    Joined:
    Sep 5, 2012
    Messages:
    3
    Update: Its not a problem with the RAM. The pins that are stuck at gnd or vcc are internal to the megawizard function. (Note that they are not the same as the names on the entity declaration).

    So you can either ignore them or suppress the warnings.
    To suppress the warnings go to:

    Assignments -> Settings -> EDA Tool settings -> Formal Verification

    And select 'None'.

    Problem solved!!......
    Davg, May 20, 2014
    #3
  4. Davg

    professor_dikweed

    Joined:
    May 24, 2014
    Messages:
    1
    DAVG! MY SAVIOR!!(although i didnt actually change the setting it was on none)

    but now that equals thing is not happening, but the 'sensitivity list thing still is. any idea what that is?
    professor_dikweed, May 24, 2014
    #4
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