Problem with vhdl records

Discussion in 'Hardware' started by kamboj, Jun 17, 2010.

  1. kamboj

    kamboj

    Joined:
    Jun 17, 2010
    Messages:
    1
    I have a DUT which have records in it

    package clk_reset_record_pkg is
    type clks is record
    clk: std_logic_vector(4 downto 0);
    end record;
    type resets is record
    reset: std_logic_vector(4 downto 0);
    end record;
    end clk_reset_record_pkg;

    library ieee; -- Library declaration
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    use work.clk_reset_record_pkg.all;
    entity top is
    port(clk_in :in clks;
    clk_enable : in std_logic;


    Now i want to instatiate this dut in my testbench. Tesbench also have same kind of record.

    dut:entity work.top(rtl) port map (clk_in => clk_record,
    clk_enable => clk_enable,
    reset_in => rst_record,


    and also use configuration to replace the instatiation as

    configuration tb_cfg_rtl of tb is
    for test
    for dut: top
    use entity work.top1(rtl);
    end for;
    end for;
    end tb_cfg_rtl;


    I am getting error
    Type mismatch for port "clk_in" in component "top" when binding to entity "top1".
    Type mismatch for port "reset_in" in component "top" when binding to entity "top1".


    It works fine when used without configuration. Is there some another construct in configuration to handle records type ?
    Can some body help on this issue.

    Regards
    Pankaj
    kamboj, Jun 17, 2010
    #1
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