Pipeline Floating point ALU

Discussion in 'Software' started by techlife3, Apr 9, 2007.

  1. techlife3

    techlife3

    Joined:
    Apr 9, 2007
    Messages:
    3
    Hi,

    I am designing a pipelined ALU for floating point numbers in IEEE format.

    I am using VHDL to code in Xilinx environment and Modelsim to simulate.

    When I give a series of inputs for addition as

    1, 1
    2, 2
    3, 3
    4, 4
    5, 5
    6, 6
    7, 7
    8, 8...............up to 21

    I am expecting a result like this
    2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42

    I am getting results like this....
    2 6 4 10 12 14 8 18 20 22 24 26 28 30 32 34 36 38 40 42

    I am getting twenty outputs in which there is a swapping for 4, 8, 16, 32....
    which are in positions 2, 4, 8, 16.......

    Can anybody make any guesses why it is happening so?

    Thanks and Regards,
    Drew
    techlife3, Apr 9, 2007
    #1
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  2. techlife3

    shabdita

    Joined:
    Mar 30, 2011
    Messages:
    1
    Hi
    I would really like the design of a pipelined ALU for floating point numbers in IEEE format. Could you please help me out.
    shabdita, Mar 30, 2011
    #2
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