Nested FOR loops in VHDL...

Discussion in 'Hardware' started by yokeshr, Dec 16, 2008.

  1. yokeshr

    yokeshr

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    Dec 16, 2008
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    sshhh...
    Hi people...

    I designed a generic parallel CRC generator and i used nested for loops for tat...When simulated, there is no prob with this... But synthesis doesn't procede at all... Some said nested FOR loops sre not synthsizable... On googlin, I couldn find a constraint like tat... Can anyone help me wit this...

    Thanks and Regards,
    Yokesh
    yokeshr, Dec 16, 2008
    #1
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