Intel’s “Sandy Bridge†Architecture

Discussion in 'NZ Computing' started by Lawrence D'Oliveiro, Sep 30, 2010.

  1. The two major new features are the “decoded uop†cache (sort of an “L0â€
    cache sitting above the existing L1 instruction cache, but containing
    instructions decoded into “uop†form, rather than the original instruction
    bytes), and a rearchitected “reorder buffer†for handling out-of-order
    instruction execution.

    Instruction reordering is a vital part of getting high performance out of
    contemporary desktop workloads. Unfortunately, the hardware for doing it is
    very power-intensive, which is why ARM chips didn’t support it until
    recently (I think their Cortex A8/A9 chips were the first to add it). It’s
    also a differentiating feature left out of the Atom chips. Notice I said
    desktop; it looks like server applications are moving in a completely
    different direction.

    <http://arstechnica.com/business/news/2010/09/intels-next-must-have-upgrade-a-look-at-sandy-bridge.ars>
    Lawrence D'Oliveiro, Sep 30, 2010
    #1
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