Help required in interpreting the 'Timeout' field in parallel port's EPP mode.

Discussion in 'Computer Information' started by amitsheth@gmail.com, Aug 25, 2006.

  1. Guest

    Hi All,
    I am working on the parallel port and need some help with the EPP mode
    of operation. I am referring to a copy of "Parallel Port Complete" by
    Jan Axelson as well as a copy of the IEEE 1284-1994 spec.

    I have a couple of issues that I need some help with:

    1. As given on page 270 of "Parallel Port Complete", the timeout
    measurement in case of an EPP mode address-write cycle starts at the
    falling edge of nIOW (which is a signal on the ISA interface) and ends
    at the rising edge of nWait.

    Nowhere in the spec have they mentioned this timeout duration.

    Can someone please tell me that apart from the nIOW signal, can the
    timeout measurement start at the toggling of any other signal on the
    parallel port's interface itself (signals which are a part of the
    parallel interface, and not on some bus like ISA) ?

    Put another way, is there any method to measure this timeout duration
    by watching a(ny) signal(s) on the port itself ?

    2. The book (Axelson) says that when a EPP timeout is detected, the 0th
    bit in the Status register (S0) is set to 1 (presumably by the port's
    hardware). I wish to know how is the status of this bit known to the
    host, i.e., is there any interrupt generated when the S0 bit is set, or
    is there any polling mechanism by the associated driver software ?

    If someone could give me some insight in these issues, I'd be really
    grateful.

    Best regards,
    Amit.
    , Aug 25, 2006
    #1
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  2. The timeout duration is the watchdog timer (~10uS). The cycle ends either
    with the nWait acknowledgement or the watchdog timer timing out. If control
    is returned and the timeout bit is set, then the timer timed out and nWait
    never happened.
    So the procedure is for the driver to write the address, and (after an
    unknown number of wait states, of which it isn't aware) check the timeout
    bit. If it's clear, the driver continues with the data write. If it's set
    the driver decides whether or not to try again, clearing the bit and
    counting the re-tries until (presumably) eventually deciding to give up.
    --
    Jeff Richards
    MS MVP (Windows - Shell/User)
    <> wrote in message
    news:...
    > Hi All,
    > I am working on the parallel port and need some help with the EPP mode
    > of operation. I am referring to a copy of "Parallel Port Complete" by
    > Jan Axelson as well as a copy of the IEEE 1284-1994 spec.
    >
    > I have a couple of issues that I need some help with:
    >
    > 1. As given on page 270 of "Parallel Port Complete", the timeout
    > measurement in case of an EPP mode address-write cycle starts at the
    > falling edge of nIOW (which is a signal on the ISA interface) and ends
    > at the rising edge of nWait.
    >
    > Nowhere in the spec have they mentioned this timeout duration.
    >
    > Can someone please tell me that apart from the nIOW signal, can the
    > timeout measurement start at the toggling of any other signal on the
    > parallel port's interface itself (signals which are a part of the
    > parallel interface, and not on some bus like ISA) ?
    >
    > Put another way, is there any method to measure this timeout duration
    > by watching a(ny) signal(s) on the port itself ?
    >
    > 2. The book (Axelson) says that when a EPP timeout is detected, the 0th
    > bit in the Status register (S0) is set to 1 (presumably by the port's
    > hardware). I wish to know how is the status of this bit known to the
    > host, i.e., is there any interrupt generated when the S0 bit is set, or
    > is there any polling mechanism by the associated driver software ?
    >
    > If someone could give me some insight in these issues, I'd be really
    > grateful.
    >
    > Best regards,
    > Amit.
    >
    Jeff Richards, Aug 25, 2006
    #2
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