Help needed in reversing keys for aes_decrpyption algorithm

Discussion in 'General Computer Support' started by abde, Jan 24, 2010.

  1. abde

    abde

    Joined:
    Jan 24, 2010
    Messages:
    1
    Hello everybody,



    I am trying to read keys (1 to 10) as input, store it in a ram (memory) and write it out in the reverse order with respect to the rounds ie. for 1st round, 10th key should be printed. I am doing this for reversing keys in aes_decryption crpytographic algorithm. I have tried in all the possible methods but could not succeed in running the code successfully. Could someone help me in that?



    CODE:



    library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    use IEEE.Numeric_Std.all;

    entity ram_dec is
    port (
    clock : in std_logic;
    we : in std_logic;
    address : in std_logic_vector(3 downto 0);
    datain : in std_logic_vector(127 downto 0);
    roundkey : out std_logic_vector(127 downto 0);
    round : in std_logic_vector(3 downto 0)
    );
    end entity ram_dec;

    architecture RTL of ram_dec is

    type ram_type is array (0 to 9) of std_logic_vector(127 downto 0);
    signal ram : ram_type;
    signal read_address : std_logic_vector(3 downto 0);
    -- signal rnd : bit_vector(3 downto 0);

    begin

    RamProc: process(clock) is

    begin
    if rising_edge(clock) then
    if we = '1' then
    -- for i in 1 to 10 loop
    ram(to_integer(unsigned(read_address))) <= datain;
    -- rnd <= std_logic_vector(unsigned(round) + 1);

    -- read_address <= std_logic_vector(unsigned(read_address) + 1);
    -- end loop;
    end if;

    -- elsif rising_edge(clock) then
    elsif we = '0' then
    -- read_address <= address;
    -- for j in 10 downto 1 loop
    case round is
    when "0000" => read_address <= "1001";
    when "0001" => read_address <= "1000";
    when "0010" => read_address <= "0111";
    when "0011" => read_address <= "0110";
    when "0100" => read_address <= "0101";
    when "0101" => read_address <= "0100";
    when "0110" => read_address <= "0011";
    when "0111" => read_address <= "0010";
    when "1000" => read_address <= "0001";
    when "1001" => read_address <= "0000";
    when others => read_address <= "0000";
    end case;

    roundkey <= ram(to_integer(unsigned(read_address)));
    -- end if;
    -- end loop;
    -- else
    -- roundkey <= X"00000000000000000000000000000000";
    end if;
    end process RamProc;

    end architecture RTL;



    This is the code. I have tried writing a test bench for this but the roundkey output stays 'U' always. I searched for possible solutions in the net and tried converting std_logic_vector to bit_vector but unsigned was not supported for bit_vector and found that I will have to otherwise make sure that all std_logic values should not have values other than '0' or '1'. So, I tried assigning values to it in test bench but did not help. I will also copy my test bench. Could someone tell if my assignment is right or what else should I change in my code as I am somewhat new to VHDL programming.



    -- TestBench Template

    library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    use IEEE.Numeric_Std.all;


    ENTITY testbench IS
    END testbench;

    ARCHITECTURE behavior OF testbench IS

    -- Component Declaration
    component ram_dec is
    port (
    clock : in std_logic;
    we : in std_logic;
    address : in std_logic_vector(3 downto 0);
    datain : in std_logic_vector(127 downto 0);
    roundkey : out std_logic_vector(127 downto 0);
    round : in std_logic_vector(3 downto 0)
    );
    end component;

    signal clock : std_logic:= '0';
    signal we : std_logic:= '0';
    signal read_address : std_logic_vector(3 downto 0):= "0000";
    signal datain : std_logic_vector(127 downto 0):= X"00000000000000000000000000000000";
    signal roundkey: std_logic_vector(127 downto 0):= X"00000000000000000000000000000000";
    signal round : std_logic_vector(3 downto 0):= "0000";

    BEGIN

    -- Component Instantiation
    uut: ram_dec PORT MAP(
    clock => clock,
    we => we,
    address => read_address,
    datain => datain,
    roundkey => roundkey,
    round => round
    );

    ClockGen: process is
    begin
    -- while not StopClock loop
    for i in 1 to 1000 loop
    clock <= '0';
    wait for 1 ns;
    clock <= '1';
    wait for 1 ns;
    end loop;
    wait;
    end process ClockGen;


    -- Test Bench Statements
    tb : PROCESS
    BEGIN
    -- roundkey <= X"00000000000000000000000000000000";

    wait for 10 ns; -- wait until global set/reset completes
    we <= '1';
    datain <= X"00010203050607080A0B0C0D0F101112";
    round <= "0000";
    wait for 4 ns;
    datain <= X"14151617191A1B1C1E1F202123242526";
    round <= "0001";
    wait for 4 ns;
    datain <= X"28292A2B2D2E2F30323334353738393A";
    round <= "0010";
    wait for 4 ns;
    datain <= X"3C3D3E3F41424344464748494B4C4D4E";
    round <= "0011";
    wait for 4 ns;
    datain <= X"50515253555657585A5B5C5D5F606162";
    round <= "0100";
    wait for 4 ns;
    datain <= X"64656667696A6B6C6E6F707173747576";
    round <= "0101";
    wait for 4 ns;
    datain <= X"78797A7B7D7E7F80828384858788898A";
    round <= "0110";
    wait for 4 ns;
    datain <= X"8C8D8E8F91929394969798999B9C9D9E";
    round <= "0111";
    wait for 4 ns;
    datain <= X"A0A1A2A3A5A6A7A8AAABACADAFB0B1B2";
    round <= "1000";
    wait for 4 ns;
    datain <= X"B4B5B6B7B9BABBBCBEBFC0C1C3C4C5C6";
    round <= "1001";
    wait for 4 ns;



    -- To print the data out

    we <= '0';
    round <= "0000";
    wait for 4 ns;
    round <= "0011";
    wait for 4 ns;
    round <= "1000";
    wait for 4 ns;
    round <= "1001";
    wait;

    END PROCESS tb;


    END;



    Thanks in advance,
    abde, Jan 24, 2010
    #1
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