Effect of variables on place and route

Discussion in 'Hardware' started by Anjana Nair, Nov 29, 2007.

  1. Anjana Nair

    Anjana Nair

    Joined:
    Nov 29, 2007
    Messages:
    1
    Hi
    I would like to know the effect on Place and Route (FPGA), if I replace a signal with a variable (VHDL) in a process.

    Thanks in advance
    Anjana.
     
    Anjana Nair, Nov 29, 2007
    #1
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