Dual Edge Serial Shift Register in VHDL

Discussion in 'Hardware' started by kapsy_27, Sep 9, 2011.

  1. kapsy_27

    kapsy_27

    Joined:
    Sep 9, 2011
    Messages:
    1
    Hi guys,
    I am new to this forum. I want to shift 16-bit data serially on both the edges of clock,
    currently I have designed a FSM for achieving this but I am not getting the desired
    frequency. Say I want to shift the data serially on both edges at 5MHz but by my design
    the frequency is 500KHz, since the FSM is running on 5MHz. Can any boady help me, I want to serially shift 16-bit data on both the edges of clock and the clock is running at 5MHz. Please Help.....!

    Thanks in advance
     
    kapsy_27, Sep 9, 2011
    #1
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. ohaqqi

    VHDL sll shift question

    ohaqqi, Oct 16, 2006, in forum: Hardware
    Replies:
    5
    Views:
    23,072
    tranhuuthu991990
    May 13, 2012
  2. amirster

    Writing Register code in vhdl

    amirster, Jun 5, 2007, in forum: Hardware
    Replies:
    2
    Views:
    2,327
    asicvlsi
    Jun 11, 2007
  3. becool_nikks
    Replies:
    0
    Views:
    2,020
    becool_nikks
    Mar 6, 2009
  4. Ian

    Lenovo ThinkPad EDGE 13: Bleeding Edge

    Ian, Feb 28, 2011, in forum: Front Page News
    Replies:
    0
    Views:
    1,178
  5. deepak21

    shift left/shift right in VHDL

    deepak21, May 6, 2012, in forum: Software
    Replies:
    0
    Views:
    1,638
    deepak21
    May 6, 2012
Loading...

Share This Page