Dlatch with mem. plz help for module and testbench

Discussion in 'The Lounge' started by dvdeepak, Mar 26, 2010.

  1. dvdeepak

    dvdeepak

    Joined:
    Mar 26, 2010
    Messages:
    2
    Dlatch with mem.Verilog. plz help for module and testbench

    hi.
    can any one help me for D-latch's module and testbench.in this figure,file attatched rd/wrd and clk are inputs and data is an inout. if rd/wrb is low then flip-flop is in write mode ;data are an input line;data on data line are written into latch when clk is positive. when rd/wrb is high , flip-flop is in read mode, data stored in latch are made available on data line.[​IMG] .

    Thanx
     

    Attached Files:

    Last edited: Mar 26, 2010
    dvdeepak, Mar 26, 2010
    #1
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  2. dvdeepak

    dvdeepak

    Joined:
    Mar 26, 2010
    Messages:
    2
    can anyone plz tell me whts wrong with the 2 methods tht i tried and are not working for the above figure.

    1st method
    module Dlatchwithmemnew2(q, data, rw,clk); ///////// its not working , data and q are giving X as ouput
    output q;
    inout data;
    input rw,clk;
    wire en,qb;
    reg d;
    reg data_out;
    wire data_in=data; /// i tried to put the data input into data_in
    Dlatch g1(q,qb,d,en); //// its a D latch with output q and qb

    assign data=(rw==1)?data_out:data_in; /// to use the inout data
    assign en=(rw==0)?clk:1'b1; //// if rw=1 then clk will always be 1 so tht when q wil b given as input to D-latch again and will b written into it


    always @( clk, rw , data, q, data_in) begin
    if (rw==1)
    begin
    data_out=q; /// output of d-latch is given into data_out
    d=q; /// q will be given as input to d-latch again
    end
    else
    begin
    data_out=q;
    d=data_in; /// data_in will be given as input to d-latch
    end
    end


    endmodule


    2nd method tht i tried is .. data is not giving proper output even by using some temp_data as reg and then substituting its value into inout data
    module main(data, rw,ck);
    inout data;
    input rw,ck; ///////////if we run the synthesis of main then there is error in tri0 and tri1
    wire wren,q,qb;//////////////but its test runs absolutely fine only by making the "data" as reg in test
    tri0 en;//////////////////// not as a wire
    tri1 d;/////////////////////whereas it should be wire coz of being an INOUT
    not(wren,rw);
    bufif1(d,data,wren);
    bufif0(en,ck,rw);
    Dlatch g1(q,qb,d,en);
    bufif1 (data,q,rw);


    endmodule



    Regards,
    Deepak.
     
    dvdeepak, Apr 2, 2010
    #2
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