Data transferred over a bridge on the falling edge of clock

Discussion in 'Hardware' started by debayan_p, May 14, 2014.

  1. debayan_p

    debayan_p

    Joined:
    Jun 2, 2009
    Messages:
    2
    Dear all,

    I am debugging a data-conversion bridge. Here one of the input signals is connected inside the bridge directly to an output signal on the other of the bridge. There are no registered or combinatorial paths for this connection.

    I have a VHDL stmnt something like: mwait_o <= stall_i;

    However when I am running the test-bench, I see that the value of stall_i is being transferred to mwait_o at the falling edge of the clock and not immediately on the rising-edge or as soon as the value of stall_i changes (which should be the expected behavior as per my VHDL stmnt).

    Can anyone comment what could be the probable reason for this?

    Thanks,
    dpaul
    debayan_p, May 14, 2014
    #1
    1. Advertising

  2. debayan_p

    debayan_p

    Joined:
    Jun 2, 2009
    Messages:
    2
    Thread closed!

    Was a stupid mistake --- the i/p signal was missing from the sensitivity list!
    debayan_p, May 14, 2014
    #2
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Robert11
    Replies:
    1
    Views:
    638
    Aussie Bomber
    Nov 24, 2004
  2. joevan
    Replies:
    11
    Views:
    592
    Blinky the Shark
    Sep 5, 2005
  3. haydude
    Replies:
    0
    Views:
    528
    haydude
    Jun 18, 2006
  4. Theo Markettos

    VOIP over VPN over TCP over WAP over 3G

    Theo Markettos, Feb 3, 2008, in forum: UK VOIP
    Replies:
    2
    Views:
    815
    Theo Markettos
    Feb 14, 2008
  5. Ian

    Lenovo ThinkPad EDGE 13: Bleeding Edge

    Ian, Feb 28, 2011, in forum: Front Page News
    Replies:
    0
    Views:
    1,146
Loading...

Share This Page