coregen-->single port block memory

Discussion in 'Hardware' started by Roya, Jul 2, 2009.

  1. Roya

    Roya

    Joined:
    Jun 30, 2009
    Messages:
    1
    Hi, i got a single port block memory from Xilinx coregen and I initialized it by .coe file. can I read this Rom through this command R<=dout?!
    is it clear to read an output port? if not how could I do it?!
    I appreciate so much if someone help me.


    Architecture...

    signal temp: std_logic_vector(7 downto 0);
    signal dout : std_logic_vector(7 downto 0);
    ---------------------------
    --component declaration
    ---------------------------
    component rom
    port(
    clk:in std_logic;
    addr:in std_logic_vector(7 downto 0);
    dout :eek:ut std_logic_vector(7 downto 0));
    end component;


    begin


    -------------------------------
    --component configuration
    -------------------------------
    memory_instance: rom
    port map(
    clk=>clk,
    addr=>temp,
    dout=>dout);
    Roya, Jul 2, 2009
    #1
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