ARRAY(n DOWNTO 0) OF STD_LOGIC_VECTOR(m DOWNTO 0) - VHDL

Discussion in 'Hardware' started by freitass, Nov 1, 2007.

  1. freitass

    freitass

    Joined:
    Oct 31, 2007
    Messages:
    2
    Hi,

    I'm facing some dificulties when declaring an entity whit an array of std_logic_vector output port.

    I want to develop a ping pong buffer with generic width and registers size.

    I've tried three possibles "solutions" (but neither worked :hmm2: ) that are shown below with it's respective error messages:

    possible solution 1:
    Code:
    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    
    ENTITY ppbuffer IS -- ping pong buffer
    	GENERIC (SIZE : INTEGER := 8;  -- buffer size
    			 DATA : INTEGER := 8 ); -- registers size
    	TYPE buff IS ARRAY (0 TO SIZE-1) OF STD_LOGIC_VECTOR (DATA-1 DOWNTO 0);
    	PORT (enable, clk : IN STD_LOGIC;
    		  input  : IN STD_LOGIC_VECTOR (DATA-1 DOWNTO 0);
    		  output : OUT buff);
    END ppbuffer;
    error for solution 1:
    Code:
    Error (10500): VHDL syntax error at ppbuffer.vhd(16) near text "PORT";  expecting "end", or "begin", or a declaration statement
    possible solution 2:
    Code:
    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    
    PACKAGE buff IS
    	TYPE buff IS ARRAY (0 TO SIZE-1) OF STD_LOGIC_VECTOR (DATA-1 DOWNTO 0);
    END buff;
    
    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    USE work.buff.all;
    
    ENTITY ppbuffer IS -- ping pong buffer
    	GENERIC (SIZE : INTEGER := 8;  -- buffer size
    			 DATA : INTEGER := 8 ); -- data size
    	PORT (enable, clk : IN STD_LOGIC;
    		  input  : IN STD_LOGIC_VECTOR (DATA-1 DOWNTO 0);
    		  output : OUT buff);
    END ppbuffer;
    error for solution 2:
    Code:
    Error (10482): VHDL error at ppbuffer.vhd(5): object "SIZE" is used but not declared
    Error (10482): VHDL error at ppbuffer.vhd(5): object "DATA" is used but not declared
    possible solution 3:
    Code:
    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    
    PACKAGE buff IS
    	TYPE buff IS ARRAY ( NATURAL RANGE <>) OF STD_LOGIC_VECTOR ( NATURAL RANGE <>);
    END buff;
    
    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    USE work.buff.all;
    
    ENTITY ppbuffer IS -- ping pong buffer
    	GENERIC (SIZE : INTEGER := 8;  -- buffer size
    			 DATA : INTEGER := 8 ); -- data size
    	PORT (enable, clk : IN STD_LOGIC;
    		  input  : IN STD_LOGIC_VECTOR (DATA-1 DOWNTO 0);
    		  output : OUT buff(0 TO SIZE-1)(DATA-1 DOWNTO 0));
    END ppbuffer;
    error for solution 3:
    Code:
    Error (10294): VHDL Type Declaration error at ppbuffer.vhd(5): element type for array type cannot be unconstrained
    What I need is to declare a flexible port size buffer to use in a pipeline description that uses some buffers of different size. It's just like an std_logic_vector, but with vectors of std_logic inside it. I hope it's possible to describe in VHDL.

    Any help would be appreciated ;-)
     
    freitass, Nov 1, 2007
    #1
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. topi1234
    Replies:
    0
    Views:
    2,009
    topi1234
    Apr 18, 2008
  2. allsey_1987
    Replies:
    0
    Views:
    2,525
    allsey_1987
    Oct 27, 2009
  3. amrutha0303
    Replies:
    0
    Views:
    1,002
    amrutha0303
    Aug 3, 2010
  4. amrutha0303
    Replies:
    0
    Views:
    2,178
    amrutha0303
    Aug 3, 2010
  5. wsch
    Replies:
    0
    Views:
    619
Loading...

Share This Page