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VHDL signal and variable assignment

 
 
ramy
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      11-12-2013
Hi, What is the difference between the two assignments?

signal s1 : std_logic_vector(3 downto 0);
signal s2 : std_logic_vector(3 downto 0);
begin
main : process (clock, reset_n)
variable v1 : std_logic_vector(3 downto 0) := (others => '0');
variable v2 : std_logic_vector(3 downto 0) := (others => '0');
begin
if (reset_n = '0') then
s1 <= (others => '0');
s2 <= (others => '0');
elsif (clock'event and clock = '1' ) then

-- ASSIGNMENT 1
v1 := '1' + s1;
s1 <= v1;

-- ASSIGNMENT 2
s2 <= v2;
v2 := '1' + s2;

end if;
end process main;
 
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Rob Gaddi
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      11-12-2013
On Mon, 11 Nov 2013 16:29:18 -0800 (PST)
ramy <(E-Mail Removed)> wrote:

> Hi, What is the difference between the two assignments?
>
> signal s1 : std_logic_vector(3 downto 0);
> signal s2 : std_logic_vector(3 downto 0);
> begin
> main : process (clock, reset_n)
> variable v1 : std_logic_vector(3 downto 0) := (others => '0');
> variable v2 : std_logic_vector(3 downto 0) := (others => '0');
> begin
> if (reset_n = '0') then
> s1 <= (others => '0');
> s2 <= (others => '0');
> elsif (clock'event and clock = '1' ) then
>
> -- ASSIGNMENT 1
> v1 := '1' + s1;
> s1 <= v1;
>
> -- ASSIGNMENT 2
> s2 <= v2;
> v2 := '1' + s2;
>
> end if;
> end process main;


In VHDL, variable assignments (:=) take effect immediately, the way they
would in a software language like C, such that subsequent lines see the
changed value. Signal assignments (<=) take effect only at the end of
the delta cycle, which for synthesizable code is the same as saying at
the end of that run through the process. Subsequent statements in the
same process continue to see the old value; only on the next invocation
of the process will the new value be visible.

--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order. See above to fix.
 
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ramya.murali.d@gmail.com
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      11-12-2013
""In VHDL, variable assignments (:=) take effect immediately, the way they
would in a software language like C, such that subsequent lines see the
changed value. ""
What if the subsequent line is a signal assignment like in Assignment 1?

Also, in Assignment 1, is s1 a register? If yes, is setup time applicable to v1?

On Monday, November 11, 2013 4:37:19 PM UTC-8, Rob Gaddi wrote:
> On Mon, 11 Nov 2013 16:29:18 -0800 (PST)
>
> ramy wrote:
>
>
>
> > Hi, What is the difference between the two assignments?

>
> >

>
> > signal s1 : std_logic_vector(3 downto 0);

>
> > signal s2 : std_logic_vector(3 downto 0);

>
> > begin

>
> > main : process (clock, reset_n)

>
> > variable v1 : std_logic_vector(3 downto 0) := (others => '0');

>
> > variable v2 : std_logic_vector(3 downto 0) := (others => '0');

>
> > begin

>
> > if (reset_n = '0') then

>
> > s1 <= (others => '0');

>
> > s2 <= (others => '0');

>
> > elsif (clock'event and clock = '1' ) then

>
> >

>
> > -- ASSIGNMENT 1

>
> > v1 := '1' + s1;

>
> > s1 <= v1;

>
> >

>
> > -- ASSIGNMENT 2

>
> > s2 <= v2;

>
> > v2 := '1' + s2;

>
> >

>
> > end if;

>
> > end process main;

>
>
>
> In VHDL, variable assignments (:=) take effect immediately, the way they
>
> would in a software language like C, such that subsequent lines see the
>
> changed value. Signal assignments (<=) take effect only at the end of
>
> the delta cycle, which for synthesizable code is the same as saying at
>
> the end of that run through the process. Subsequent statements in the
>
> same process continue to see the old value; only on the next invocation
>
> of the process will the new value be visible.
>
>
>
> --
>
> Rob Gaddi, Highland Technology -- www.highlandtechnology.com
>
> Email address domain is currently out of order. See above to fix.

 
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rickman
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      11-12-2013
On 11/11/2013 9:32 PM, http://www.velocityreviews.com/forums/(E-Mail Removed) wrote:
> ""In VHDL, variable assignments (:=) take effect immediately, the way they
> would in a software language like C, such that subsequent lines see the
> changed value. ""
> What if the subsequent line is a signal assignment like in Assignment 1?


What line follows does not matter. A variable is updated immediately,
period, end of sentence. In example 1 v1 is updated by the assignment
before the next line is executed. So v1 takes the value '1' + S1
although I'm not sure what that means. S1 is an SLV and I don't know of
a library that defines the '+' operator for a character and an SLV. But
then I get rusty in VHDL between projects and I may just be forgetting
this one.

When the next line is executed s1 will be given the value of v1 so that
after the process exits s1 will be updated to the value that was in v1.

In example 2 the signal assignment is first so although s2 is assigned
the value of v2, it is not actually updated until the process exits,
long after v2 is updated by the subsequent statement. The assignment of
v2 happens immediately, but since s2 has not been updated v2 gets the
old value of s2.

> Also, in Assignment 1, is s1 a register? If yes, is setup time applicable to v1?


In example 1 s1 is indeed the output of a register. v1 is not the
output of a register, rather it is the output of the logic feeding
register s1, or you can think of it as the input to the register s1.

In the second example v2 is the output of a register because it is used
*before* it is assigned. That implies it must remember its value from
the last iteration of the code i.e. a register. So both s2 and v2 are
the outputs of registers.

Rick


> On Monday, November 11, 2013 4:37:19 PM UTC-8, Rob Gaddi wrote:
>> On Mon, 11 Nov 2013 16:29:18 -0800 (PST)
>>
>> ramy wrote:
>>
>>
>>
>>> Hi, What is the difference between the two assignments?

>>
>>>

>>
>>> signal s1 : std_logic_vector(3 downto 0);

>>
>>> signal s2 : std_logic_vector(3 downto 0);

>>
>>> begin

>>
>>> main : process (clock, reset_n)

>>
>>> variable v1 : std_logic_vector(3 downto 0) := (others => '0');

>>
>>> variable v2 : std_logic_vector(3 downto 0) := (others => '0');

>>
>>> begin

>>
>>> if (reset_n = '0') then

>>
>>> s1<= (others => '0');

>>
>>> s2<= (others => '0');

>>
>>> elsif (clock'event and clock = '1' ) then

>>
>>>

>>
>>> -- ASSIGNMENT 1

>>
>>> v1 := '1' + s1;

>>
>>> s1<= v1;

>>
>>>

>>
>>> -- ASSIGNMENT 2

>>
>>> s2<= v2;

>>
>>> v2 := '1' + s2;

>>
>>>

>>
>>> end if;

>>
>>> end process main;

>>
>>
>>
>> In VHDL, variable assignments (:=) take effect immediately, the way they
>>
>> would in a software language like C, such that subsequent lines see the
>>
>> changed value. Signal assignments (<=) take effect only at the end of
>>
>> the delta cycle, which for synthesizable code is the same as saying at
>>
>> the end of that run through the process. Subsequent statements in the
>>
>> same process continue to see the old value; only on the next invocation
>>
>> of the process will the new value be visible.
>>
>>
>>
>> --
>>
>> Rob Gaddi, Highland Technology -- www.highlandtechnology.com
>>
>> Email address domain is currently out of order. See above to fix.

 
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alb
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Posts: n/a
 
      11-12-2013
Hi Ramya,

On 12/11/2013 01:29, ramy wrote:
> Hi, What is the difference between the two assignments?
> signal s1 : std_logic_vector(3 downto 0);
> signal s2 : std_logic_vector(3 downto 0);
> begin
> main : process (clock, reset_n)
> variable v1 : std_logic_vector(3 downto 0) := (others => '0');
> variable v2 : std_logic_vector(3 downto 0) := (others => '0');
> begin
> if (reset_n = '0') then
> s1 <= (others => '0');
> s2 <= (others => '0');
> elsif (clock'event and clock = '1' ) then
>
> -- ASSIGNMENT 1
> v1 := '1' + s1;
> s1 <= v1;
>
> -- ASSIGNMENT 2
> s2 <= v2;
> v2 := '1' + s2;
>
> end if;
> end process main;


first of all please avoid using SLV if you need to add something to it.
Use an integer or (un)signed instead since '+' functions are
standardized in the 'numeric_std' package.

Secondly why don't you just simulate it? I actually did it and found
what I expected.

Thirdly and maybe more to the point, remember that since variables take
a value immediately, order of assignment matters. In the first case v1
is simply a combinatorial logic with a summing function which feeds the
register s1, in the second case v2 is a register which is fed by a
summing function and that is registered again with s2.

This means that in the first case you have some comb. logic and a
register, in the second case you'll have some comb. logic and two
registers, having the operation done in twice the time.

HTH,

Al
 
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alb
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      11-12-2013
Hi Rick,

On 12/11/2013 07:26, rickman wrote:
[]
S1 is an SLV and I don't know of
> a library that defines the '+' operator for a character and an SLV.


there's no 'character' involved, the operator the OP intended to use is
overloaded in std_logic_unsigned which is deprecated but unfortunately
made it through several text books (as well as std_logic_arith and
std_logic_signed).

Al
 
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rickman
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      11-13-2013
On 11/12/2013 7:44 AM, alb wrote:
> Hi Rick,
>
> On 12/11/2013 07:26, rickman wrote:
> []
> S1 is an SLV and I don't know of
>> a library that defines the '+' operator for a character and an SLV.

>
> there's no 'character' involved, the operator the OP intended to use is
> overloaded in std_logic_unsigned which is deprecated but unfortunately
> made it through several text books (as well as std_logic_arith and
> std_logic_signed).


I'm not going to argue with you about this, but the OP's code which you
trimmed was adding a character to the SLV. The character may be
interpreted as a single bit of data, but calling it a character is not
invalid. The point is that this statement without a greater context is
not valid VHDL.

v1 := '1' + s1;

--

Rick
 
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Andy
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      11-14-2013
On Monday, November 11, 2013 8:32:54 PM UTC-6, (E-Mail Removed) wrote:
> Also, in Assignment 1, is s1 a register?


In synthesizable VHDL, any reference to a signal assigned in a clocked process is usually* a reference to the output of a register. This is commonly simplified to "the signal is a register", which is usually accurate, but notalways*.

However, with a variable in a clocked process, different references to (reads of) the same variable in the same clock cycle could return different values, depending on what/when it was most recently written. Therefore, the variable itself is neither register nor combinatorial, but each reference to it would be either (the output of a) registered or combinatorial.

If the variable was (or could have been) written in the same clock cycle, but prior to the reference, then the reference is combinatorial.

If the variable was not (and could not have been) written in the same clockcycle prior to the reference, then the reference is registered.

In the case when a variable may or may not have been written in the same clock cycle prior to the reference, the same condition that determines whether the prior write ocurred also controls an implied multiplexer which selects either the combinatorial value feeding the register, or the register output. Thus the output is combinatorial (the output of the multiplexer).

*The above is for assignments and references to variables and signals inside the clocked if/elsif-statement. A reference to a variable AFTER the end of the clocked if/elsif-statement is always registered. More importantly, signals assigned from an expression of variables after the end of the clockedif/elsif statement are the combinatorial result of the expressed logic after the variables' registers. This is the only way to generate a combinatorial output signal directly from a clocked process.

If this seems confusing, just remember that the synthesis tool will create a circuit that mimics the clock-cycle behavior of the executed code. If it takes an extra clock cycle for a value to propagate through the process, then the synthesis tool will use a register to create that extra clock cycle delay.

Andy
 
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