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Verilog warning - output pins are stuck at GND

 
 
KyoukaNg KyoukaNg is offline
Junior Member
Join Date: Oct 2013
Location: melaka
Posts: 1
 
      10-13-2013
Hi,

I've a few of questions.
After i compile my verilog code in quartus2, the are warnings written as "output pins are stuck at GND". How can i solve this? Is it necessary to solve all the warning?

My code is like this
################################################## ###########################
always@*
if (reset)
output = 0;
################################################## ###########################
 
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