Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > confusion about delta time

Reply
Thread Tools

confusion about delta time

 
 
sensor
Guest
Posts: n/a
 
      08-15-2013
Hi. When I was simulating a design of cripple adder using Modelsim, I found the list output hard to understand. Code of the design was copied from <<Circuit Design with VHDL>> by Volnei A. Pedroni.


-- adder_cripple.vhd

library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------
entity adder_cripple is
generic(n: integer := 4);
port (a, b: in std_logic_vector(n-1 downto 0);
cin: in std_logic;
s: out std_logic_vector(n-1 downto 0);
cout: out std_logic);
end adder_cripple;
-------------------------------------------------
architecture adder of adder_cripple is
signal c: std_logic_vector(n downto 0);
begin
c(0) <= cin;
g1: for i in 0 to n-1 generate
s(i) <= a(i) xor b(i) xor c(i);
c(i+1) <= ( a(i) and b(i) ) or
( a(i) and c(i) ) or
( b(i) and c(i) );
end generate g1;
cout <= c(n);
end adder;
-------------------------------------------------


-- testbench

-------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------
entity adder_tb is
generic (m: integer := 4);
end;
-------------------------------------------------
architecture adder_tb1 of adder_tb is
component adder_cripple is
generic(n: integer := 4);
port(a, b: in std_logic_vector(n-1 downto 0);
cin: in std_logic;
s: out std_logic_vector(n-1 downto 0);
cout: out std_logic);
end component adder_cripple;
signal a, b: std_logic_vector(m-1 downto 0);
signal cin: std_logic;
signal s: std_logic_vector(m-1 downto 0);
signal cout: std_logic;
begin
UUT: adder_cripple
generic map(n => m)
port map(
a => a,
b => b,
cin => cin,
s => s,
cout => cout);

a_proc: process
begin
a <= "0011";
wait for 200 ns;
a <= "0110";
wait;
end process a_proc;

b_proc: process
begin
b <= "1000";
wait for 120 ns;
b <= "1100";
wait;
end process b_proc;

cin_proc: process
begin
cin <= '0';
wait for 200 ns;
cin <= '1';
wait;
end process cin_proc;
end adder_tb1;

-------------------------------------------------





list output:

ns | delta | a | b | cin | s | cout |
----|--------|------|------|-----|------|------|
0 | +0 | UUUU | UUUU | U | UUUU | U |
0 | +1 | 0011 | 1000 | 0 | UUUU | U |
0 | +3 | 0011 | 1000 | 0 | 1UU1 | U |
0 | +4 | 0011 | 1000 | 0 | 1U11 | 0 |
0 | +5 | 0011 | 1000 | 0 | 1011 | 0 |
120 | +1 | 0011 | 1100 | 0 | 1011 | 0 |
120 | +2 | 0011 | 1100 | 0 | 1111 | 0 |
200 | +1 | 0110 | 1100 | 1 | 1111 | 0 |
200 | +2 | 0110 | 1100 | 1 | 1010 | 0 |
200 | +3 | 0110 | 1100 | 1 | 0011 | 0 |
200 | +4 | 0110 | 1100 | 1 | 0011 | 1 |
----|--------|------|------|-----|------|------|


Why s(3) is computed together with s(0) at 0 ns + 3 delta? Any help will be appretiated. Thx.
 
Reply With Quote
 
 
 
 
centeno.jose.manuel@gmail.com
Guest
Posts: n/a
 
      08-15-2013
Hi.

The answer is probably short -circuit operators.

"The operators and, or, nand and nor are called short-circuit operators, as they only evaluate the right operand if the left operand does not determine the result. For example, if the left operand of the and operator isfalse, we know that the result is false, so we do not need to consider theother operand."

Ashenden, Peter J. (2010-10-07). The Designer's Guide to VHDL (p. 46). Elsevier Science (book series). Kindle Edition.


Your test case has something special on a(2) and b(2) at delta 0.

On Thursday, August 15, 2013 11:06:18 AM UTC-5, sensor wrote:
> c(i+1) <= ( a(i) and b(i) ) or
>
> ( a(i) and c(i) ) or
>
> ( b(i) and c(i) );


-- On delta 1 a b and cin are already assigned.
Most c(i) values need other c values to be calculated, except for c(0) and c(2).c(0) can be calculated from cin. c(2) can be calculated directly from a(2) and b(2). Let's take a look.

c(i+1) <= ( a(i) and b(i) ) or ( a(i) and c(i) ) or ( b(i) and c(i) );
-- For i = 2
c(3) <= ( a(2) and b(2) ) or ( a(2) and c(2) ) or ( b(2) and c(2) );
-- Substitute a and b since those are known at delta 1.
c(3) <= ( 0 and 0 ) or ( 0 and c(2) ) or ( 0 and c(2) );
-- Values on c(2) are ignored by the "and" operator because the left parameter is 0.
c(3) <= 0;
-- Delta cycle 1 ends. c(3) gets a 0 on delta cycle 2 and triggers other assignments, such as s(3) <= a(3) xor b(3) xor c(3);



I hope this helps.

 
Reply With Quote
 
 
 
 
sensor
Guest
Posts: n/a
 
      08-16-2013
在 2013年8月16日星期五UTC+8上午3时08分58秒 ,(E-Mail Removed)写道:
> Hi. The answer is probably short -circuit operators. "The operators and, or, nand and nor are called “short-circuit” operators, as they only evaluate the right operand if the left operand does not determine the result. For example, if the left operand of the and operator is false, we know that the result is false, so we do not need to consider the other operand." Ashenden, Peter J. (2010-10-07). The Designer's Guide to VHDL (p. 46). Elsevier Science (book series). Kindle Edition. Your test case has something special on a(2) and b(2) at delta 0. On Thursday, August 15, 2013 11:06:18 AM UTC-5, sensor wrote: > c(i+1) <= ( a(i) and b(i) ) or > > ( a(i) and c(i) ) or > > ( b(i) and c(i) ); -- On delta 1 a b and cin are already assigned. Most c(i) values need other c values to be calculated, except for c(0) and c(2).c(0) can be calculated from cin. c(2) can be calculated directly from a(2) and b(2). Let's take a look. c(i+1) <= ( a(i) and b(i) )or ( a(i) and c(i) ) or ( b(i) and c(i) ); -- For i = 2 c(3) <= ( a(2)and b(2) ) or ( a(2) and c(2) ) or ( b(2) and c(2) ); -- Substitute a and b since those are known at delta 1. c(3) <= ( 0 and 0 ) or ( 0 and c(2) )or ( 0 and c(2) ); -- Values on c(2) are ignored by the "and" operator because the left parameter is 0. c(3) <= 0; -- Delta cycle 1 ends. c(3) getsa 0 on delta cycle 2 and triggers other assignments, such as s(3) <= a(3) xor b(3) xor c(3); I hope this helps.



I've got it. Thanks a lot.
 
Reply With Quote
 
sensor
Guest
Posts: n/a
 
      08-16-2013
在 2013年8月16日星期五UTC+8上午4时44分39秒 ,Alan Fitch写道:
> On 15/08/13 20:08, http://www.velocityreviews.com/forums/(E-Mail Removed) wrote: > Hi. > > The answer is probably short -circuit operators. > <snip> Also if you don't want to see the deltas, you can use the List options in Modelsim and set "Collapse deltas". That will show you the last value of the signal just before timeadvances - in other words what you see on a typical waveform viewer, regards Alan -- Alan Fitch


Thank you for replying.
 
Reply With Quote
 
Paul Uiterlinden
Guest
Posts: n/a
 
      08-16-2013
Alan Fitch wrote:

> On 15/08/13 20:08, (E-Mail Removed) wrote:
>> Hi.
>>
>> The answer is probably short -circuit operators.
>>

>
> <snip>
>
> Also if you don't want to see the deltas, you can use the List options
> in Modelsim and set "Collapse deltas". That will show you the last value
> of the signal just before time advances - in other words what you see on
> a typical waveform viewer,


And if you do want to see deltas but find the list window a bit awkward, you
can expand deltas in the wave from viewer (at least in ModelSim).

--
P@u!
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
silly question about Running a script from the command line A.Rock Python 0 04-10-2013 11:21 AM
newbie question about confusing exception handling in urllib cabbar@gmail.com Python 6 04-09-2013 07:11 PM
Delta Time sridar VHDL 0 12-03-2010 08:41 AM
delta cycle?? (delta delay) srikanth.padava VHDL 0 02-28-2008 09:01 AM
delta time = time stop - time start engsol Python 2 01-26-2004 12:06 PM



Advertisments