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Re: random numbers

 
 
Andy
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      08-13-2013
On Monday, September 16, 2002 10:55:02 AM UTC-5, itsme wrote:
> Hi,I like to write a techbench whichuses random numbers for
> input data to test my hardware.Does VHDL has a built in
> random number generator? Is there any library?


Peter,

There is a new vhdl library called Open Source VHDL Verification Methodology availabe at OSVVM.org, along with user guides, and a support blog & forum..

The library provides mechanisms (protected type function/procedure calls) for constrained random stimulus generation, and functional coverage management. You can even use the coverage management to directly control the randomization constraints in the stimulus generation if desired. It is a great alternative to SystemVerilog UVM.

OSVVM is written and supported by Jim Lewis of Synthworks, who is a frequent poster here, and an ardent supporter of VHDL.

Andy
 
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