Velocity Reviews > VHDL > if statement problem

# if statement problem

Bart Fox
Guest
Posts: n/a

 07-24-2013
Am 24.07.13 20:17, schrieb lokesh kumar:
> for i in 8 downto 5 loop
> if b(i) = '1' then
> (temp(i) downto temp (i-5)) <= (b(i) downto b(i-5)) xor "100101";
> else if b(i) = '0';
> null;
> end if;
> end loop;
> c <= (temp(4) downto temp(0));

\$ ghdl -a test.vhd
test.vhd:1:2: entity, architecture, package or configuration keyword
expected
test.vhd:1:2: design file is empty (no design unit found)

ieee' and ends with 'end architechture'

regards,
Bart

lokesh kumar
Guest
Posts: n/a

 07-24-2013

entity squr_5bit is
Port ( a : in STD_LOGIC_VECTOR (4 downto 0);
c : out STD_LOGIC_VECTOR (8 downto 0));
end squr_5bit;

architecture Behavioral of squr_5bit is
signal b : STD_LOGIC_VECTOR (8 downto 0);
signal temp : STD_LOGIC_VECTOR (8 downto 0);
begin
position_even_b: for i in 0 to 4 generate b(2*i) <= a(i);
end generate;
c <= b;
position_odd_b: for i in 0 to 3 generate b(2*i+1) <= '0';
end generate;

-- position_c:for i in 8 downto 5 loop
--if b(i) = '1' then
--(temp(i) downto temp (i-5)) <= (b(i) downto b(i-5)) xor "100101";
-- else if b(i) = '0';
--null;
--end if;
--end loop;
--c <= (temp(4) downto temp(0));
end Behavioral;
----------------------------------
This is the full code. I am taking a 5-bit number. And making its square. (Please note that the final addition is not a simple binary addition, its anXOR operation). So the output will be a 9-bit number. It suppose, A = a4a3 a2 a1 a0 then then output always come as, C = a4 0 a3 0 a2 0 a1 0 a0 (in this manner)
Now I need to reduce the output to 5-bit number.

suppose the square is, 101010101
For reduction, I have to use 100101.

101010101
100101
---------
001111101 (XOR operation)
Now I have to check if the MSB is "1" or not. If the MSB is "1" then I have to do the XOR operation in same way. But if the MSB is zero, then I have to check the second MSB.
Like that I have to do the loop for 4-times to get the 5-bit reduction result.
-----
I am getting an error. It shows "Unexpected error For loop"

Andy
Guest
Posts: n/a

 07-24-2013
Every entry-level VHDL text book states that for-loops are sequential statements and must be in a process or subprogram (function/procedure).

Andy

Paul Uiterlinden
Guest
Posts: n/a

 07-29-2013
lokesh kumar wrote:

>
> entity squr_5bit is
> Port ( a : in STD_LOGIC_VECTOR (4 downto 0);
> c : out STD_LOGIC_VECTOR (8 downto 0));
> end squr_5bit;
>
> architecture Behavioral of squr_5bit is
> signal b : STD_LOGIC_VECTOR (8 downto 0);
> signal temp : STD_LOGIC_VECTOR (8 downto 0);
> begin
> position_even_b: for i in 0 to 4 generate b(2*i) <= a(i);
> end generate;
> c <= b;
> position_odd_b: for i in 0 to 3 generate b(2*i+1) <= '0';
> end generate;
>
> -- position_c:for i in 8 downto 5 loop
> --if b(i) = '1' then
> --(temp(i) downto temp (i-5)) <= (b(i) downto b(i-5)) xor "100101";
> -- else if b(i) = '0';
> --null;
> --end if;
> --end loop;
> --c <= (temp(4) downto temp(0));
> end Behavioral;

If you want a slice of a vector, it is temp(4 downto 0) instead of
(temp(4) downto temp(0)).

--
Paul Uiterlinden
AimValley