On Saturday, July 20, 2013 1:39:08 PM UTC+5:30, rickman wrote:

> On 7/19/2013 11:38 PM, Gabor wrote:

>

> > On 7/19/2013 6:23 PM, Fredxx wrote:

>

> >> On 19/07/2013 18:27, lokesh kumar wrote:

>

> >>> Hi,

>

> >>>

>

> >>> Can anyone help me to design a code to square binary number?

>

> >>>

>

> >>> Suppose "A" is a 5 bit number (a4a3a2a1a0)

>

> >>>

>

> >>> If we do A x A then the output result will be "0 a4 0 a3 0 a2 0 a1 0

>

> >>> a0 " ( a 10 bit number)

>

> >>

>

> >> All these numbers look bigger than 5 or 10 bits!

>

> >>

>

> >

>

> > The syntax is not VHDL. He means for A to be a 5-bit vector

>

> > and the result ended up as:

>

> > '0' & A(4) $ '0' & A(3) $ '0' & A(2) $ '0' & A(1) $ '0' & A(0)

>

> >

>

> >>>

>

> >>> For example : Suppose A= 11111

>

> >>> Then A x A = 11111 x 11111 = 0101010101 ( Xor operation is done for

>

> >>> the adding to get the final result).

>

> >>

>

> >> 31 x 31 = 961 (11 1100 0001)

>

> >>

>

> >> So clearly XORing is incorrect.

>

> >>

>

> >

>

> > For the OP clearly "multiplication" or "squaring" is incorrect. He

>

> > apparently wants a different function that is similar to multiplication

>

> > but lacks any carries on the intermediate addition.

>

> >

>

> >>> Could anyone please help me out how to make a generalized code for

>

> >>> squaring of a 5-bit number to get an output like this?

>

> >>>

>

> >>

>

> >> A square operation is precisely that, A * A. Most FPGAs have some

>

> >> pretty good multipliers, best to use them.

>

>

>

> If he is doing a calculation on a polynomial, I understand why he wants

>

> a multiply with no carries. Each term of the polynomial has a

>

> coefficient which is all the terms of the same value summed together mod

>

> 2 (XOR). But I don't understand his other statements. As you showed

>

> earlier his general form above for the product is not accurate. Or he

>

> is saying something we don't understand.

>

>

>

> From what I understand (or think I understand) this should be code he

>

> could use.

>

>

>

> subtype binary_num_5 is std_logic_vector (4 downto 0);

>

> signal A : binary_num_5;

>

> signal B : binary_num_5;

>

>

>

> function square (arg : std_logic_vector) return std_logic_vector is

>

> constant arg_Hi : integer := arg'HIGH;

>

> constant arg_Lo : integer := arg'LOW;

>

> constant arg_Len : integer := arg'LENGTH;

>

> variable prod : std_logic_vector ((arg_Hi + arg_Len) downto arg_L)

>

> := (others => '0');

>

> begin

>

> for i in arg'range loop

>

> prod := prod XOR std_logic_vector (

>

> SHIFT_LEFT (RESIZE (unsigned(arg), 2*arg_Len), i));

>

> end loop;

>

> return prod;

>

> end square;

>

>

>

> ...

>

>

>

> B <= square (A);

>

>

>

>

>

> I think this will do the job but I haven't tested it, so many errors can

>

> be present! If nothing else, it should give a good idea on how to

>

> proceed. I will say the whole thing is a little bit simpler if it is

>

> done with unsigned type signals rather than std_logic_vector. This

>

> would eliminate the type casts in the loop assignment statement.

>

>

>

> prod := prod XOR SHIFT_LEFT (RESIZE (arg, 2*arg_Len), i));

>

>

>

> --

>

>

>

> Rick
library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

--use work.my_package.all;

entity square_163_7_6_3 is

port (

a: in std_logic_vector(162 downto 0);

z: out std_logic_vector(162 downto 0)

);

end square_163_7_6_3;

architecture circuit of square_163_7_6_3 is

signal s, t, u, s_plus_t: std_logic_vector(162 downto 0);

signal xor1, xor2: std_logic;

begin

vector_s: for i in 0 to 80 generate s(2*i) <= a(i); s(2*i + 1) <= a(i+82); end generate;

s(162) <= a(81);

vector_t1: for j in 0 to 6 generate t(j) <= '0'; end generate;

t(7) <= a(82);

vector_t2: for i in 4 to 80 generate t(2*i) <= a(i+7

; t(2*i + 1) <= a(i+79); end generate;

t(162) <= a(159);

xor1 <= a(160) xor a(161); xor2 <= a(161) xor a(162);

u(0) <= a(160); u(1) <= a(160) xor a(162); u(2) <= a(161); u(3) <= xor1;

u(4) <= a(82) xor a(160); u(5) <= xor2; u(6) <= a(83) xor xor1;

u(7) <= '0'; u(

<= a(84) xor xor1; u(9) <= '0'; u(10) <= a(85) xor xor2;

u(11) <= '0'; u(12) <= a(86) xor a(162);

u(13) <= '0';

vector_u: for i in 7 to 80 generate u(2*i) <= a(i+80); u(2*i + 1) <= '0'; end generate;

u(162) <= a(161);

xor_gates1: for j in 0 to 162 generate s_plus_t(j) <= s(j) xor t(j); end generate;

xor_gates2: for j in 0 to 162 generate z(j) <= s_plus_t(j) xor u(j); end generate;

end circuit;

This the the exact code I found online, I think. But it is for 163-bit. So it is difficult to test and verify. Can you please help me to convert it for a 5-bit to make me understand it?

Many Thanks!