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Newbie question on combining if rising_edge(clk).

 
 
valtih1978
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      07-16-2013

wait until clk = '1';

requires less typing than

if clk = '1' then
end if;

and, furthremore, causes less confusion than the conditional. I wonder
why people keep reproducing this awkward IF pattern instead of wait
until. Single wait until synthesizes well, even in xilinx tools now.
I've checked that may times.
 
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rickman
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      07-16-2013
On 7/16/2013 8:47 AM, valtih1978 wrote:
>
> wait until clk = '1';
>
> requires less typing than
>
> if clk = '1' then
> end if;
>
> and, furthremore, causes less confusion than the conditional. I wonder
> why people keep reproducing this awkward IF pattern instead of wait
> until. Single wait until synthesizes well, even in xilinx tools now.
> I've checked that may times.


What is the related code for an async resettable FF?

--

Rick
 
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goouse99@gmail.com
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      07-17-2013
Am Dienstag, 16. Juli 2013 14:47:49 UTC+2 schrieb valtih1978:
> wait until clk = '1';
>
>
>
> requires less typing than
>
>
>
> if clk = '1' then
>
> end if;
>
>
>
> and, furthremore, causes less confusion than the conditional. I wonder
>
> why people keep reproducing this awkward IF pattern instead of wait
>
> until. Single wait until synthesizes well, even in xilinx tools now.
>
> I've checked that may times.


Hi,
wait until clk = '1';

actually creates latches, which most of us are trying to avoid.

What you probably mean is:

wait until rising_edge(clk);

And to answer rickmans question too:
Yes this coding style makes it hard, if not impossible to implement a (async) reset.
However, there are many applications that neither need this.
There's also this famous paper from Xilinx suggestiong to avoid async resets when possible.
But of course, if one needs it, the well known
if reset then
elsif rising_edge(clk)
does the job pretty well, and for thos who whant to save time typing code:
Use EMACS with VHDL mode.
Then 90% of the code is writing itself.
Just make sure you have a reliable TAB button on your keyboard.

Have a nice synthesis
Eilert

 
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valtih1978
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      07-17-2013
What is the problem? Can you be more specific?

Should I care using the async pattern because async reset is depricated
and I never use it? Why should I care about the related code?

Is it the only argument you have?
 
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valtih1978
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      07-17-2013
Rising_edge(clk) is basically equivalent to

process
wait on clk; -- implied by sensetivity list
if clk'event and clk = '1' then
<body>
end if;

end process;

whereas wait until clk='1' is equivalent to (see VHDL spec)

process
loop
wait on Clk;
exit when Clk = '1';
end loop;
<body>
end process

Tell me the difference. I see waiting for the edge in both cases. Does
latch mean the edge-sensitive storage? So, might be it is your
rising_edge that produces the latch? Why double standards?

Do you say that bad style is popular because people mistakenly think
that good style produces the latches?


 
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rickman
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      07-17-2013
On 7/17/2013 5:58 AM, valtih1978 wrote:
> What is the problem? Can you be more specific?
>
> Should I care using the async pattern because async reset is depricated
> and I never use it? Why should I care about the related code?
>
> Is it the only argument you have?


I'm asking how you would use this form to generate an async reset on the
FF. Who exactly has "deprecated" the async reset? If you never use it,
that's fine, but I design FPGAs which use an async reset. If you don't
specify a reset the register value is defaults to zero in most cases. I
prefer to define a reset value because it can be useful and it makes the
synthesis match the simulation.

I see no advantage to this form. It may be fewer keystrokes, but my
design process is not limited by the number keys I press. I type very
fast. If I waw worried about the number of keys I press, I wouldn't be
using VHDL at all.

--

Rick
 
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valtih1978
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      07-17-2013
It is not just a number of keystrokes. You have extra IF-then nest to
handle, which complicates the structure of your code whereas wait until
just makes the wait for clk edge explicit. But, thanks for the argument.
 
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Andy
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      07-17-2013
On Wednesday, July 17, 2013 10:04:36 AM UTC-5, valtih1978 wrote:
> It is not just a number of keystrokes. You have extra IF-then nest to handle, which complicates the structure of your code whereas wait until just makes the wait for clk edge explicit. But, thanks for the argument.


It would be "safer" to use "wait until rising_edge(clk)", since "wait untilclk = '1';" will trigger if clk changes from 'H' to '1' (not a rising edge), and will not trigger when clk changes from '0' to 'H' (a rising edge).For the synthesis tool it won't matter, but the RTL simulation will matter, potentially causing a simulation mismatch between RTL and gate level simulations.

If you need asynchronous reset (not a matter of choice for some design domains), then you'd have to wait for either/both of two events, and then you'dhave to use an if-statement to figure out which condition triggered the wait statement.

BTW, an exit statement with a condition is equivalent to an if statement containing an unconditional exit statement. There are no free lunches.

Also, the implicit wait statement in a process with a sensitivity list is at the BOTTOM of the process, not at the top. No real difference for synthesis, but there are differences in simulation: all processes run at startup, regardless of the sensitivity list. Wait statements will not trigger at startup.

Andy


 
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Rob Gaddi
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      07-17-2013
On Tue, 16 Jul 2013 22:45:20 -0700 (PDT)
http://www.velocityreviews.com/forums/(E-Mail Removed) wrote:

> Am Dienstag, 16. Juli 2013 14:47:49 UTC+2 schrieb valtih1978:
> > wait until clk = '1';
> >
> >
> >
> > requires less typing than
> >
> >
> >
> > if clk = '1' then
> >
> > end if;
> >
> >
> >
> > and, furthremore, causes less confusion than the conditional. I wonder
> >
> > why people keep reproducing this awkward IF pattern instead of wait
> >
> > until. Single wait until synthesizes well, even in xilinx tools now.
> >
> > I've checked that may times.

>
> Hi,
> wait until clk = '1';
>
> actually creates latches, which most of us are trying to avoid.
>
> What you probably mean is:
>
> wait until rising_edge(clk);
>
> And to answer rickmans question too:
> Yes this coding style makes it hard, if not impossible to implement a (async) reset.
> However, there are many applications that neither need this.
> There's also this famous paper from Xilinx suggestiong to avoid async resets when possible.
> But of course, if one needs it, the well known
> if reset then
> elsif rising_edge(clk)
> does the job pretty well, and for thos who whant to save time typing code:
> Use EMACS with VHDL mode.
> Then 90% of the code is writing itself.
> Just make sure you have a reliable TAB button on your keyboard.
>
> Have a nice synthesis
> Eilert
>


I think this is one of the rare instances where you're wrong.
wait until clk = '1';
is equivalent to
wait on clk until clk = '1';
which is the same as
wait until rising_edge(clk)
if clk can only be '0' or '1'.

Likewise the OP's
if clk = '1' then
in a process where clk was the only thing in the sensitivity list
should have the same behavior as any of that, or of the more traditional
if rising_edge(clk) then

I've used the "wait until" form in synthesizable code a couple times.
It seems to work, at least on modern synthesizers, and it's nice to save
one level of indentation, but it's not a huge deal one way or another.
It does make an async reset pretty impossible, for what that's worth in
whichever circumstances.

I think my biggest problem with it stylistically is that it's simply
not canonical. The synthesizer can take in all manner of things that,
handed off to someone who didn't write them, would cause
consternation. The goal of writing code is to produce something that
not only performs correctly, but is intuitively and obviously correct
to anyone who sits down to read it. Part of that is doing commonly
done things in the way they're commonly done.

--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order. See above to fix.
 
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rickman
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      07-17-2013
On 7/17/2013 11:04 AM, valtih1978 wrote:
> It is not just a number of keystrokes. You have extra IF-then nest to
> handle, which complicates the structure of your code whereas wait until
> just makes the wait for clk edge explicit. But, thanks for the argument.


Yeah, I understand what you are saying. I just don't consider any of
these advantages to be addressing problems I have when writing VHDL.

process (clk, reset inputs)
begin
IF (reset condition) then
reset assignments...
ELSIF (rising_edge(clk)) then
register assignments...
ENDIF;
end process;

This is just a form that is so common and recognizable that I have never
given any thought to the need to save a line or two or an indentation
level.

I have seen the form below used for simple FFs.

data_out <= data_in when rising_edge(clk);

This is the simplest form I am familiar with, one line, no indents! The
problem with the concurrent FF statement is that it is harder to add
much logic. The FF input signal would need to be defined by other
statements if the logic is very complex at all.

Of the three forms, I prefer to just use the clocked process and keep
the form constant. No one is confused and the registers are always
easily recognized.

BTW, I have not read the synthesis standard. Does that mention all
three of these forms? Does the standard say anything about
initialization in the signal declaration? That might make a big
difference in which forms are acceptable or preferred.

--

Rick
 
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