Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Webinar: VHDL Intelligent Coverage using Open Source VHDLVerification Methodology (OSVVM), July 18

Thread Tools

Webinar: VHDL Intelligent Coverage using Open Source VHDLVerification Methodology (OSVVM), July 18

Jim Lewis
Posts: n/a
Date: Thursday, July 18, 2013

OSVVM Europe Session, 3-4 PM CEST (6-7 AM PDT)
OSVVM US Session, 11 am - 12 Noon PDT

Presented by:
Jim Lewis, SynthWorks VHDL Training Expert, IEEE 1076 Working Group Chair, and OS-VVM Chief Architect

At the lowest level, Open Source VHDL Verification Methodology (OSVVM), is a set of packages that provide concise and powerful methods to implement functional coverage and randomization. OS-VVM uses these packages to create an intelligent testbench methodology that allows mixing of "Intelligent Coverage™" with directed, algorithmic, file based, or constrained random testapproaches. Having an intelligent testbench approach built into the coverage modeling puts OS-VVM a step ahead of other verification methodologies, such as SystemVerilog and UVM.

Attend this webinar and learn how to utilize OSVVM to add functional coverage, Intelligent Coverage, and constrained random methods to your current testbench.

What and Why OSVVM, Functional Coverage, and Randomization
Writing Item (Point Coverage)
Writing Cross Coverage
Constrained Random is 5X or More Slower
Intelligent Coverage
OS-VVM is More Capable
Additional Randomization in OS-VVM
Weighted Intelligent Coverage
Coverage Closure
OS-VVM Loves any Testbench
Additional Methods for Verification

Benefits of OSVVM include:
Faster Test Construction, focus is on functional coverage
Faster simulations: O(Log N) faster than constrained random and no solver.
Goes beyond other verification languages (SystemVerilog and 'e')
Works with your current VHDL testbench
Uses entity and architectures for structure (just like RTL).
Is language accessible. Able to refine with code.
Readable by ALL (Verification and RTL engineers).

OSVVM is open-source package based. It compiles under VHDL-2008 or VHDL-2002(with minor adaptations), so you can use it today. See
Reply With Quote

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off

Similar Threads
Thread Thread Starter Forum Replies Last Post
Announcing release of OSVVM 2013.04 Jim Lewis VHDL 0 05-01-2013 08:26 PM
Open Source VHDL Verification Methodology HT-Lab VHDL 4 02-27-2012 11:34 AM
Code coverage & Functional coverage tutorials Raj VHDL 4 02-21-2008 12:32 PM "Statement coverage is the weakest measure of code coverage" Ben Finney Python 7 10-30-2007 01:43 PM
[Announce]DataDirect XQuery Webinar Tomorrow (Thursday July 20) XML 0 07-19-2006 03:39 PM