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Distributed Ram with Initial Values (Virtex)

 
 
kevin.neilson@xilinx.com
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      06-21-2013
If you want to target BRAM, you have to have at least one cycle of latency,since the BRAM address is registered. (Distributed RAM can be fully combinatorial.) The tools will then target BRAM if it's over a certain (small) depth. You can add synthesis directives, but you probably don't need them.
 
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Andy
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      06-24-2013
On Thursday, June 20, 2013 7:37:47 PM UTC-5, (E-Mail Removed) wrote:
> If you want to target BRAM, you have to have at least one cycle of latency, since the BRAM address is registered. (Distributed RAM can be fully combinatorial.) The tools will then target BRAM if it's over a certain (small) depth. You can add synthesis directives, but you probably don't need them.


Depending on the target device, block RAM read data may be registered instead of (or in addition to) the address being registered. Most synthesis tools don't care, as long as there is one cycle of latency between address and read data.

I have not tried this on a device that had both distributed and block rams,but if you describe RAM accesses with 1 cycle latency on reads, then it should use block rams first, then it should switch to distributed rams plus registers.

You can also use an attribute on the array to direct the ram style. See your synthesis tool documentation for details.

Andy
 
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